| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Fixes related to handling of autowires and upto-ranges, fixes #814 | Clifford Wolf | 2019-02-21 | 1 | -2/+2 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix segfault in printing of some internal error messages | Clifford Wolf | 2019-02-21 | 1 | -2/+2 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix sign handling of real constants | Clifford Wolf | 2019-02-13 | 1 | -5/+4 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Various indenting fixes in AST front-end (mostly space vs tab issues) | Clifford Wolf | 2018-11-04 | 1 | -55/+33 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Improve read_verilog range out of bounds warning | Clifford Wolf | 2018-10-20 | 1 | -6/+6 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Refactor code to avoid code duplication + added comments | Ruben Undheim | 2018-10-20 | 1 | -21/+4 | |
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| * | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 1 | -5/+7 | |
| | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport) | |||||
| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+29 | |
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| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -2/+46 | |
| | | | | | This time doing the changes mostly in AST before RTLIL generation | |||||
| * | Fix for issue 594. | Tom Verbeure | 2018-10-02 | 1 | -1/+2 | |
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| * | Convert more log_error() to log_file_error() where possible. | Henner Zeller | 2018-07-20 | 1 | -71/+69 | |
| | | | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion. | |||||
| * | Use log_file_warning(), log_file_error() functions. | Henner Zeller | 2018-07-20 | 1 | -16/+16 | |
| | | | | | Wherever we can report a source-level location. | |||||
| * | Provide source-location logging. | Henner Zeller | 2018-07-19 | 1 | -3/+2 | |
| | | | | | | | | | o Provide log_file_warning() and log_file_error() that prefix the log message with <filename>:<lineno>: to be easily picked up by IDEs that need to step through errors. o Simplify some duplicate logging code in kernel/log.cc o Use the new log functions in genrtlil. | |||||
| * | Fix handling of signed memories | Clifford Wolf | 2018-06-28 | 1 | -0/+3 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add (* gclk *) attribute support | Clifford Wolf | 2018-06-01 | 1 | -0/+9 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -2/+2 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix error handling for nested always/initial | Clifford Wolf | 2017-12-02 | 1 | -0/+2 | |
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| * | Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵ | Clifford Wolf | 2017-06-07 | 1 | -0/+7 | |
| | | | | | const reg" | |||||
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -1/+6 | |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+2 | |
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| * | Some fixes in handling of signed arrays | Clifford Wolf | 2016-11-01 | 1 | -0/+1 | |
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| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 1 | -2/+2 | |
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| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 1 | -4/+11 | |
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| * | Added $past, $stable, $rose, $fell SVA functions | Clifford Wolf | 2016-09-19 | 1 | -0/+10 | |
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| * | Added assertpmux | Clifford Wolf | 2016-09-07 | 1 | -0/+1 | |
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| * | Added $anyconst support to yosys-smtbmc | Clifford Wolf | 2016-08-30 | 1 | -0/+2 | |
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| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 1 | -3/+3 | |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -2/+0 | |
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| * | Another bugfix in mem2reg code | Clifford Wolf | 2016-08-21 | 1 | -0/+2 | |
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| * | Optimize memory address port width in wreduce and memory_collect, not ↵ | Clifford Wolf | 2016-08-19 | 1 | -4/+8 | |
| | | | | | verilog front-end | |||||
| * | Only allow posedge/negedge with 1 bit wide signals | Clifford Wolf | 2016-08-10 | 1 | -0/+2 | |
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| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 1 | -0/+45 | |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -2/+2 | |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -2/+7 | |
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| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 1 | -0/+1 | |
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| * | Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b} | Clifford Wolf | 2016-05-27 | 1 | -0/+11 | |
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| * | fixed typos in error messages | Clifford Wolf | 2016-05-27 | 1 | -3/+3 | |
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| * | Fixed handling of parameters and const functions in casex/casez pattern | Clifford Wolf | 2016-04-21 | 1 | -2/+4 | |
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| * | Fixed some visual studio warnings | Clifford Wolf | 2016-02-13 | 1 | -1/+1 | |
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| * | genrtlil: avoid converting SigSpec to set<SigBit> when going through ↵ | Rick Altherr | 2016-01-31 | 1 | -3/+3 | |
| | | | | | removeSignalFromCaseTree() | |||||
| * | Fixed handling of parameters and localparams in functions | Clifford Wolf | 2015-11-11 | 1 | -0/+5 | |
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| * | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -20/+20 | |
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| * | Added read-enable to memory model | Clifford Wolf | 2015-09-25 | 1 | -0/+1 | |
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| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -7/+7 | |
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| * | Added WORDS parameter to $meminit | Clifford Wolf | 2015-07-31 | 1 | -1/+9 | |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 | |
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| * | Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker() | Clifford Wolf | 2015-03-01 | 1 | -2/+4 | |
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| * | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 | 1 | -4/+7 | |
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| * | Convert floating point cell parameters to strings | Clifford Wolf | 2015-02-18 | 1 | -9/+12 | |
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| * | Various fixes for memories with offsets | Clifford Wolf | 2015-02-14 | 1 | -6/+4 | |
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