iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add $allconst and $allseq cell types	Clifford Wolf	2018-02-23	1	-2/+2
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Fix error handling for nested always/initial	Clifford Wolf	2017-12-02	1	-0/+2
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*	Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵	Clifford Wolf	2017-06-07	1	-0/+7
\| \| \| \|	const reg"
*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	1	-1/+6
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*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	1	-0/+2
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*	Some fixes in handling of signed arrays	Clifford Wolf	2016-11-01	1	-0/+1
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*	Added $anyseq cell type	Clifford Wolf	2016-10-14	1	-2/+2
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*	Added $global_clock verilog syntax support for creating $ff cells	Clifford Wolf	2016-10-14	1	-4/+11
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*	Added $past, $stable, $rose, $fell SVA functions	Clifford Wolf	2016-09-19	1	-0/+10
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*	Added assertpmux	Clifford Wolf	2016-09-07	1	-0/+1
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*	Added $anyconst support to yosys-smtbmc	Clifford Wolf	2016-08-30	1	-0/+2
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*	Removed $aconst cell type	Clifford Wolf	2016-08-30	1	-3/+3
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*	Removed $predict again	Clifford Wolf	2016-08-28	1	-2/+0
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*	Another bugfix in mem2reg code	Clifford Wolf	2016-08-21	1	-0/+2
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*	Optimize memory address port width in wreduce and memory_collect, not ↵	Clifford Wolf	2016-08-19	1	-4/+8
\| \| \| \|	verilog front-end
*	Only allow posedge/negedge with 1 bit wide signals	Clifford Wolf	2016-08-10	1	-0/+2
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*	Added $anyconst and $aconst	Clifford Wolf	2016-07-27	1	-0/+45
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*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	1	-2/+2
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*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-2/+7
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*	Added support for SystemVerilog packages with localparam definitions	Ruben Undheim	2016-06-18	1	-0/+1
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*	Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}	Clifford Wolf	2016-05-27	1	-0/+11
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*	fixed typos in error messages	Clifford Wolf	2016-05-27	1	-3/+3
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*	Fixed handling of parameters and const functions in casex/casez pattern	Clifford Wolf	2016-04-21	1	-2/+4
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*	Fixed some visual studio warnings	Clifford Wolf	2016-02-13	1	-1/+1
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*	genrtlil: avoid converting SigSpec to set<SigBit> when going through ↵	Rick Altherr	2016-01-31	1	-3/+3
\| \| \| \|	removeSignalFromCaseTree()
*	Fixed handling of parameters and localparams in functions	Clifford Wolf	2015-11-11	1	-0/+5
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*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-20/+20
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*	Added read-enable to memory model	Clifford Wolf	2015-09-25	1	-0/+1
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*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-7/+7
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*	Added WORDS parameter to $meminit	Clifford Wolf	2015-07-31	1	-1/+9
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
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*	Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()	Clifford Wolf	2015-03-01	1	-2/+4
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*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26	1	-4/+7
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*	Convert floating point cell parameters to strings	Clifford Wolf	2015-02-18	1	-9/+12
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*	Various fixes for memories with offsets	Clifford Wolf	2015-02-14	1	-6/+4
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*	Creating $meminit cells in verilog front-end	Clifford Wolf	2015-02-14	1	-6/+9
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*	Ignore explicit assignments to constants in HDL code	Clifford Wolf	2015-02-08	1	-0/+14
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*	Fixed a bug with autowire bit size	Clifford Wolf	2015-02-08	1	-9/+3
\| \| \| \|	(removed leftover from when we tried to auto-size the wires)
*	Fixed memory->start_offset handling	Clifford Wolf	2015-01-01	1	-6/+7
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*	Changed more code to dict<> and pool<>	Clifford Wolf	2014-12-28	1	-3/+3
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*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-1/+1
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*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-6/+6
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*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-8/+8
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*	Fixed assignment of out-of bounds array element	Clifford Wolf	2014-09-06	1	-2/+26
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-5/+5
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*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21	1	-0/+1
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*	Improved AST ProcessGenerator performance	Clifford Wolf	2014-08-17	1	-3/+3
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*	Use stackmap<> in AST ProcessGenerator	Clifford Wolf	2014-08-17	1	-21/+19
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*	AST ProcessGenerator: replaced subst__{from,to} with subst__map	Clifford Wolf	2014-08-16	1	-41/+26
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*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14	1	-11/+3
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