| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | Fixed issue #630 by fixing a minor typo in the previous commit | Udi Finkelstein | 2018-09-25 | 1 | -2/+2 | |
| | | | | | | | | | (as well as a non critical minor code optimization) | |||||
| | * | Merge branch 'master' into pr_reg_wire_error | Udi Finkelstein | 2018-09-18 | 1 | -123/+121 | |
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| | * | | Fixed remaining cases where we check fo wire reg/wire incorrect assignments | Udi Finkelstein | 2018-09-18 | 1 | -0/+12 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule | |||||
| * | | | Add read_verilog $changed support | Dan Gisselquist | 2018-10-01 | 1 | -1/+4 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Fix handling of $past 2nd argument in read_verilog | Clifford Wolf | 2018-09-30 | 1 | -1/+1 | |
| | |/ |/| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #590 from hzeller/remaining-file-error | Clifford Wolf | 2018-08-15 | 1 | -15/+15 | |
| |\ \ | | | | | | | Fix remaining log_file_error(); emit dependent file references in new… | |||||
| | * | | Fix remaining log_file_error(); emit dependent file references in new line. | Henner Zeller | 2018-07-20 | 1 | -15/+15 | |
| | | | | | | | | | | | | | | | | | | | | | | There are some places that reference dependent file locations ("this function was called from ..."). These are now in a separate line for ease of jumping to it with the editor (behaves similarly to compilers that emit dependent messages). | |||||
| * | | | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 1 | -0/+42 | |
| |\ \ \ | |/ / |/| / | |/ | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test) | |||||
| | * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -6/+38 | |
| | | | | | | | | | No longer false warnings for memories and assertions | |||||
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -0/+10 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) | |||||
| * | | Convert more log_error() to log_file_error() where possible. | Henner Zeller | 2018-07-20 | 1 | -54/+53 | |
| | | | | | | | | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion. | |||||
| * | | Use log_file_warning(), log_file_error() functions. | Henner Zeller | 2018-07-20 | 1 | -61/+60 | |
| |/ | | | | Wherever we can report a source-level location. | |||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add support for "yosys -E" | Clifford Wolf | 2018-01-07 | 1 | -0/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix error handling for nested always/initial | Clifford Wolf | 2017-12-02 | 1 | -0/+3 | |
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| * | Remove some dead code | Clifford Wolf | 2017-10-10 | 1 | -15/+0 | |
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| * | Allow $past, $stable, $rose, $fell in $global_clock blocks | Clifford Wolf | 2017-10-10 | 1 | -1/+5 | |
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| * | Allow $size and $bits in verilog mode, actually check test case | Clifford Wolf | 2017-09-29 | 1 | -1/+1 | |
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| * | $size() now works correctly for all cases! | Udi Finkelstein | 2017-09-26 | 1 | -17/+17 | |
| | | | | | It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly. | |||||
| * | $size() seems to work now with or without the optional parameter. | Udi Finkelstein | 2017-09-26 | 1 | -10/+40 | |
| | | | | | Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated. | |||||
| * | enable $bits() and $size() functions only when the SystemVerilog flag is ↵ | Udi Finkelstein | 2017-09-26 | 1 | -1/+1 | |
| | | | | | enabled for read_verilog | |||||
| * | Added $bits() for memories as well. | Udi Finkelstein | 2017-09-26 | 1 | -2/+26 | |
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| * | $size() now works with memories as well! | Udi Finkelstein | 2017-09-26 | 1 | -1/+3 | |
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| * | Add $size() function. At the moment it works only on expressions, not on ↵ | Udi Finkelstein | 2017-09-26 | 1 | -0/+14 | |
| | | | | | memories. | |||||
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -2/+2 | |
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| * | Fix incorrect "incompatible re-declaration of wire" error in tasks/functions | Clifford Wolf | 2017-02-14 | 1 | -2/+9 | |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -2/+2 | |
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| * | Fix bug in AstNode::mem2reg_as_needed_pass2() | Clifford Wolf | 2017-01-15 | 1 | -0/+2 | |
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| * | Fixed handling of local memories in functions | Clifford Wolf | 2017-01-05 | 1 | -2/+2 | |
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| * | Added handling of local memories and error for local decls in unnamed blocks | Clifford Wolf | 2017-01-04 | 1 | -1/+10 | |
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| * | Added Verilog $rtoi and $itor support | Clifford Wolf | 2017-01-03 | 1 | -24/+30 | |
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| * | Added support for hierarchical defparams | Clifford Wolf | 2016-11-15 | 1 | -11/+32 | |
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| * | Fixed anonymous genblock object names | Clifford Wolf | 2016-11-04 | 1 | -1/+1 | |
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| * | Some fixes in handling of signed arrays | Clifford Wolf | 2016-11-01 | 1 | -0/+6 | |
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| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 1 | -2/+2 | |
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| * | Added $past, $stable, $rose, $fell SVA functions | Clifford Wolf | 2016-09-19 | 1 | -2/+131 | |
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| * | Avoid creation of bogus initial blocks for assert/assume in always @* | Clifford Wolf | 2016-09-06 | 1 | -1/+11 | |
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| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 1 | -2/+2 | |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -2/+2 | |
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| * | Fixed bug with memories that do not have a down-to-zero data width | Clifford Wolf | 2016-08-22 | 1 | -2/+13 | |
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| * | Another bugfix in mem2reg code | Clifford Wolf | 2016-08-21 | 1 | -6/+28 | |
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| * | Fixed finish_addr handling in $readmemh/$readmemb | Clifford Wolf | 2016-08-20 | 1 | -3/+3 | |
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| * | Optimize memory address port width in wreduce and memory_collect, not ↵ | Clifford Wolf | 2016-08-19 | 1 | -0/+5 | |
| | | | | | verilog front-end | |||||
| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 1 | -0/+4 | |
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| * | Using $initstate in "initial assume" and "initial assert" | Clifford Wolf | 2016-07-21 | 1 | -1/+6 | |
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| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 1 | -0/+24 | |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -2/+2 | |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -5/+7 | |
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| * | Fixed mem assignment in left-hand-side concatenation | Clifford Wolf | 2016-07-08 | 1 | -0/+44 | |
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| * | Fixed access-after-delete bug in mem2reg code | Clifford Wolf | 2016-05-27 | 1 | -6/+22 | |
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