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* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-14/+14
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* | kernel: use more ID::*Eddie Hung2020-04-021-2/+2
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* | Merge pull request #1848 from YosysHQ/eddie/fix_dynsliceClaire Wolf2020-04-011-1/+1
|\| | | | | ast: simplify to fully populate dynamic slicing case transformation
| * ast: simplify to fully populate dynamic slicing case transformationEddie Hung2020-03-311-1/+1
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* | Merge pull request #1607 from whitequark/simplify-simplify-meminitClaire Wolf2020-03-271-63/+82
|\ \ | | | | | | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
| * | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.whitequark2020-02-071-65/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
* | | Fix NDEBUG warningsEddie Hung2020-03-191-1/+1
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* | | Add precise locations for assertshuaixv2020-03-191-0/+1
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* | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-132/+130
|\ \ | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * | Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-132/+130
| | | | | | | | | | | | and RTLIL nodes.
* | | Merge pull request #1681 from YosysHQ/eddie/fix1663Claire Wolf2020-03-031-15/+13
|\ \ \ | | | | | | | | verilog: instead of modifying localparam size, extend init constant expr
| * | | verilog: instead of modifying localparam size, extend init constant exprEddie Hung2020-02-051-15/+13
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* | | Comment out log()Eddie Hung2020-02-271-1/+1
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* | Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-201-11/+187
|\ \ | | | | | | Enum support
| * | remove unnecessary blank lineJeff Wang2020-02-171-2/+1
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| * | add attributes for enumerated values in ilangJeff Wang2020-02-171-1/+67
| | | | | | | | | | | | | | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
| * | separate out enum_item/param implementation when they should be differentJeff Wang2020-02-171-7/+16
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| * | fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6Jeff Wang2020-01-171-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | The if(str == node->str) is in fact necessary (otherwise causes generate for in Multiplier_2D in tests/simple/multiplier.v to fail with error message "Right hand side of 3rd expression of generate for-loop is not constant!"). Note: in PeterCrozier's implementation, the break only breaks out of the switch-case, not the outer for loop.
| * | fix enum in generate blocksJeff Wang2020-01-161-0/+20
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| * | allow enums to be declared at toplevel scopeJeff Wang2020-01-161-0/+7
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| * | partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-161-11/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* | | Modified $readmem[hb] to use '\' or '/' according the OSRodrigo Alejandro Melo2020-02-061-1/+6
| | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
* | | Merge branch 'master' of https://github.com/YosysHQ/yosysRodrigo Alejandro Melo2020-02-031-93/+109
|\ \ \ | | |/ | |/| | | | | | | | | | Solved a conflict into the CHANGELOG Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * | ast: Add support for $sformatf system functionDavid Shah2020-01-191-93/+109
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Replaced strlen by GetSize into simplify.ccRodrigo Alejandro Melo2020-02-031-2/+2
| | | | | | | | | | | | As recommended in CodingReadme. Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
* | Fixed a bug in the new feature of $readmem[hb] when an empty string is providedRodrigo Alejandro Melo2020-02-011-1/+1
| | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* | Modified the new search for files of $readmem[hb] to be backward compatibleRodrigo Alejandro Melo2020-01-311-3/+7
| | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* | $readmem[hb] file inclusion is now relative to the Verilog fileRodrigo Alejandro Melo2020-01-311-1/+2
|/ | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* Stray log_dumpEddie Hung2019-12-111-1/+0
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* Preserve size of $genval$-s in for loopsEddie Hung2019-12-111-0/+17
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* frontends/ast: code styleDavid Shah2019-10-031-2/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Fix typedefs in blocksDavid Shah2019-10-031-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Add support for memories of a typedefDavid Shah2019-10-031-6/+20
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Add support for memory typedefsDavid Shah2019-10-031-2/+15
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Fix typedefs in packagesDavid Shah2019-10-031-4/+10
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Fix typedef parametersDavid Shah2019-10-031-2/+31
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-5/+46
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix handling of range selects on loop variables, fixes #1372Clifford Wolf2019-09-161-2/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Properly construct $live and $fair cells from "if (...) assume/assert ↵Clifford Wolf2019-09-021-7/+18
| | | | | | | | (s_eventually ...)" Fixes https://github.com/YosysHQ/SymbiYosys/issues/59 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Do not propagate mem2reg attribute through to resultEddie Hung2019-08-221-1/+2
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* mem2reg to preserve user attributes and srcEddie Hung2019-08-211-0/+4
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* substr() -> compare()Eddie Hung2019-08-071-3/+3
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* Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-071-15/+2
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| * Fix handling of functions/tasks without top-level begin-end block, fixes #1231Clifford Wolf2019-08-061-15/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
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* Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-061-0/+1
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| * Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Re-enable "final loop assignment" featureClifford Wolf2019-05-011-2/+0
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Disabled "final loop assignment" featureClifford Wolf2019-04-301-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add final loop variable assignment when unrolling for-loops, fixes #968Clifford Wolf2019-04-301-0/+7
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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