iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	4	-3/+22
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*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13	1	-4/+2
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*	Sign-extension related fixes in SatGen and AST frontend	Clifford Wolf	2013-06-10	1	-0/+2
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*	Fixes and improvements in AST const folding	Clifford Wolf	2013-06-10	2	-1/+11
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*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	4	-10/+20
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*	Added log_assert() api	Clifford Wolf	2013-05-24	1	-2/+1
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*	Merge branch 'bugfix'	Clifford Wolf	2013-05-16	1	-2/+0
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\| *	Fixed synthesis of functions in latched blocks	Clifford Wolf	2013-05-16	1	-2/+0
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* \|	Fixed handling of positional module parameters	Clifford Wolf	2013-04-26	1	-6/+4
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* \|	Only use sha1 checksums for names of parametric modules when the verbose ↵	Clifford Wolf	2013-04-26	1	-9/+20
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* \|	Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵	Clifford Wolf	2013-04-13	1	-4/+4
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* \|	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31	3	-7/+31
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* \|	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	4	-2/+14
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* \|	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	2	-5/+21
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* \|	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26	1	-3/+1
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* \|	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26	2	-1/+19
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*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25	3	-34/+16
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*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	3	-10/+17
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*	Another fix in mem2reg ast simplify logic	Clifford Wolf	2013-03-24	1	-1/+3
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*	Improved mem2reg handling in ast simplifier	Clifford Wolf	2013-03-24	2	-5/+35
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*	Tiny fixes to verilog parser	Clifford Wolf	2013-03-23	1	-0/+3
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*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	3	-3/+3
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*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26	3	-1/+17
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*	initial import	Clifford Wolf	2013-01-05	5	-0/+3227