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* Fix segfault in printing of some internal error messagesClifford Wolf2019-02-211-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-2/+2
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Fix segfault in AST simplifyClifford Wolf2018-12-181-0/+5
| | | | | | (as proposed by Dan Gisselquist) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make return value of $clog2 signedSylvain Munaut2018-11-241-1/+1
| | | | | | | | As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Various indenting fixes in AST front-end (mostly space vs tab issues)Clifford Wolf2018-11-043-99/+69
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make and dependent upon LSB onlyZipCPU2018-11-031-2/+8
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* Do not generate "reg assigned in a continuous assignment" warnings for "rand ↵Clifford Wolf2018-11-011-2/+15
| | | | | | reg" Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-203-134/+108
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* Support for SystemVerilog interfaces as a port in the top level module + ↵Ruben Undheim2018-10-201-3/+105
| | | | test case
* Fixed memory leakRuben Undheim2018-10-201-0/+1
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* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-184-14/+265
|\ | | | | Support for SystemVerilog interfaces and modports
| * Documentation improvements etc.Ruben Undheim2018-10-132-8/+35
| | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
| * Fix build error with clangRuben Undheim2018-10-121-1/+1
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| * Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-123-5/+68
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| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-124-14/+175
| | | | | | | | This time doing the changes mostly in AST before RTLIL generation
* | Merge pull request #638 from udif/pr_reg_wire_errorClifford Wolf2018-10-171-0/+12
|\ \ | |/ |/| Fix issue #630
| * Fixed issue #630 by fixing a minor typo in the previous commitUdi Finkelstein2018-09-251-2/+2
| | | | | | | | (as well as a non critical minor code optimization)
| * Merge branch 'master' into pr_reg_wire_errorUdi Finkelstein2018-09-184-237/+254
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| * | Fixed remaining cases where we check fo wire reg/wire incorrect assignmentsUdi Finkelstein2018-09-181-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
* | | Fix for issue 594.Tom Verbeure2018-10-021-1/+2
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* | | Add read_verilog $changed supportDan Gisselquist2018-10-011-1/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix handling of $past 2nd argument in read_verilogClifford Wolf2018-09-301-1/+1
| |/ |/| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-232-8/+11
| | | | | | | | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same.
* | Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-151-4/+4
|\ \ | | | | | | Consistent use of 'override' for virtual methods in derived classes.
| * | Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* | | Merge pull request #590 from hzeller/remaining-file-errorClifford Wolf2018-08-151-15/+15
|\ \ \ | | | | | | | | Fix remaining log_file_error(); emit dependent file references in new…
| * | | Fix remaining log_file_error(); emit dependent file references in new line.Henner Zeller2018-07-201-15/+15
| |/ / | | | | | | | | | | | | | | | | | | There are some places that reference dependent file locations ("this function was called from ..."). These are now in a separate line for ease of jumping to it with the editor (behaves similarly to compilers that emit dependent messages).
* | | Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-153-2/+50
|\ \ \ | |/ / |/| / | |/ Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
| * Modified errors into warningsUdi Finkelstein2018-06-053-7/+40
| | | | | | | | No longer false warnings for memories and assertions
| * This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-113-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
* | Convert more log_error() to log_file_error() where possible.Henner Zeller2018-07-203-132/+128
| | | | | | | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion.
* | Use log_file_warning(), log_file_error() functions.Henner Zeller2018-07-202-77/+76
| | | | | | | | Wherever we can report a source-level location.
* | Provide source-location logging.Henner Zeller2018-07-191-3/+2
| | | | | | | | | | | | | | | | o Provide log_file_warning() and log_file_error() that prefix the log message with <filename>:<lineno>: to be easily picked up by IDEs that need to step through errors. o Simplify some duplicate logging code in kernel/log.cc o Use the new log functions in genrtlil.
* | Fix handling of signed memoriesClifford Wolf2018-06-281-0/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add (* gclk *) attribute supportClifford Wolf2018-06-011-0/+9
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-032-6/+14
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $allconst and $allseq cell typesClifford Wolf2018-02-232-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for "yosys -E"Clifford Wolf2018-01-071-0/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-052-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix error handling for nested always/initialClifford Wolf2017-12-022-0/+5
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* Remove some dead codeClifford Wolf2017-10-101-15/+0
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* Allow $past, $stable, $rose, $fell in $global_clock blocksClifford Wolf2017-10-101-1/+5
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* Turned a few member functions into const, esp. dumpAst(), dumpVlog().Udi Finkelstein2017-09-302-14/+14
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* Allow $size and $bits in verilog mode, actually check test caseClifford Wolf2017-09-291-1/+1
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* $size() now works correctly for all cases!Udi Finkelstein2017-09-261-17/+17
| | | | It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
* $size() seems to work now with or without the optional parameter.Udi Finkelstein2017-09-261-10/+40
| | | | Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
* enable $bits() and $size() functions only when the SystemVerilog flag is ↵Udi Finkelstein2017-09-261-1/+1
| | | | enabled for read_verilog
* Added $bits() for memories as well.Udi Finkelstein2017-09-261-2/+26
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