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| * | | Allow %0s $display format specifierZachary Snow2020-08-091-1/+1
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* | | Merge pull request #2338 from zachjs/const-branch-finishclairexen2020-08-181-4/+4
|\ \ \ | | | | | | | | Propagate const_fold through generate blocks and branches
| * | | Propagate const_fold through generate blocks and branchesZachary Snow2020-08-091-4/+4
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* | | Merge pull request #2317 from zachjs/expand-genblockclairexen2020-08-182-42/+83
|\ \ \ | | | | | | | | Fix generate scoping issues
| * | | Fix generate scoping issuesZachary Snow2020-07-312-42/+83
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
* | | Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into ↵Claire Wolf2020-08-181-26/+29
|\ \ \ | | | | | | | | | | | | | | | | | | | | zachjs-const-func-block-var Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Allow blocks with declarations within constant functionsZachary Snow2020-07-251-18/+21
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* | | | Merge pull request #2281 from zachjs/const-realclairexen2020-08-181-3/+11
|\ \ \ \ | |_|/ / |/| | | Allow reals as constant function parameters
| * | | Allow reals as constant function parametersZachary Snow2020-07-191-3/+11
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* | | Merge pull request #2301 from zachjs/for-loop-errorsclairexen2020-07-281-17/+19
|\ \ \ | | | | | | | | Clearer for loop error messages
| * | | Clearer for loop error messagesZachary Snow2020-07-251-17/+19
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* / / Avoid generating wires for function args which are constantZachary Snow2020-07-241-0/+28
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* | Add AST_EDGE support to AstNode::detect_latch(), fixes #2241Claire Wolf2020-07-101-0/+2
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Merge pull request #2179 from splhack/static-castclairexen2020-07-014-0/+34
|\ \ | | | | | | Support SystemVerilog Static Cast
| * | static cast: simplifyKazuki Sakamoto2020-06-191-0/+7
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| * | static cast: support changing size and signednessKazuki Sakamoto2020-06-194-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* | | Allow constant function calls in for loops and generate if and caseZachary Snow2020-06-291-1/+5
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* | | Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().whitequark2020-06-191-1/+1
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* | Use C++11 final/override keywords.whitequark2020-06-181-5/+5
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* | Merge pull request #2112 from YosysHQ/claire/fix2040clairexen2020-06-092-0/+58
|\ \ | |/ |/| Add latch detection for use_case_method in part-select write
| * Add latch detection for use_case_method in part-select write, fixes #2040Claire Wolf2020-06-042-0/+58
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Support packed arrays in struct/union.Peter Crozier2020-06-071-12/+131
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* Merge pull request #2041 from PeterCrozier/structclairexen2020-06-044-103/+310
|\ | | | | Implementation of SV structs.
| * Merge branch 'master' into structPeter Crozier2020-06-032-4/+23
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| * | Generalise structs and add support for packed unions.Peter Crozier2020-05-124-40/+109
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| * | Implement SV structs.Peter Crozier2020-05-084-103/+241
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* | | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-041-0/+1
|\ \ \ | |_|/ |/| | Preserve 'signed'-ness of a verilog wire through RTLIL
| * | Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser
* | | Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logicclairexen2020-05-291-2/+2
|\ \ \ | | | | | | | | ast/simplify: don't bitblast async ROMs declared as `logic`
| * | | ast/simplify: don't bitblast async ROMs declared as `logic`.whitequark2020-05-051-2/+2
| | | | | | | | | | | | | | | | Fixes #2020.
* | | | Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-1/+20
| | | | | | | | | | | | | | | | Fixes #2058.
* | | | Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-141-1/+1
|\ \ \ \ | |_|_|/ |/| | | ast: swap range regardless of range_left >= 0
| * | | ast: swap range regardless of range_left >= 0Eddie Hung2020-05-041-1/+1
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* | | | Merge pull request #2022 from Xiretza/fallthroughswhitequark2020-05-082-4/+5
|\ \ \ \ | | | | | | | | | | Avoid switch fall-through warnings
| * | | | Add YS_FALLTHROUGH macro to mark case fall-throughXiretza2020-05-072-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | C++17 introduced [[fallthrough]], GCC and clang had their own vendored attributes before that. MSVC doesn't seem to have such a warning at all.
* | | | | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-074-14/+80
|\ \ \ \ \ | |/ / / / |/| | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
| * | | | Fix handling of signed indices in bit slicesClaire Wolf2020-05-021-3/+8
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | | Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-024-5/+20
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵Claire Wolf2020-05-024-7/+53
| | |/ / | |/| | | | | | | | | | | | | | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | Merge pull request #2025 from YosysHQ/eddie/frontend_cleanupEddie Hung2020-05-052-13/+13
|\ \ \ \ | | | | | | | | | | frontend: cleanup to use more ID::*, more dict<> instead of map<>
| * | | | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-042-13/+13
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* / | | verilog: set src attribute for primitivesEddie Hung2020-05-041-1/+3
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* | | Merge pull request #1996 from boqwxp/rtlil_source_locationsEddie Hung2020-05-041-13/+13
|\ \ \ | |/ / |/| | frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
| * | frontend: Include complete source location instead of just ↵Alberto Gonzalez2020-05-011-13/+13
| |/ | | | | | | `location.first_line` in `frontends/ast/genrtlil.cc`.
* / Clear current_scope when done with RTLIL generation, fixes #1837Claire Wolf2020-04-221-0/+4
|/ | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-212-3/+4
| | | | Fixes #1819, #1820.
* Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-214-15/+207
|\ | | | | Improved rewrite code for writing to bit slice
| * Make mask-and-shift the default for bitselwriteClaire Wolf2020-04-161-1/+1
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-164-4/+144
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * Improved rewrite code for writing to bit slice (disabled for now)Claire Wolf2020-04-151-12/+64
| | | | | | | | | | | | | | | | | | This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-14 03:39:04 +0000