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| * | | Checking and fixing specify cells in genRTLILClifford Wolf2019-04-231-1/+15
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-062-0/+3
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| * | | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Fix width detection of memory access with bit slice, fixes #974Clifford Wolf2019-05-011-0/+2
| | |/ | |/| | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / | Re-enable "final loop assignment" featureClifford Wolf2019-05-011-2/+0
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Disabled "final loop assignment" featureClifford Wolf2019-04-301-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add final loop variable assignment when unrolling for-loops, fixes #968Clifford Wolf2019-04-301-0/+7
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Determine correct signedness and expression width in for loop unrolling, ↵Clifford Wolf2019-04-221-3/+18
| | | | | | fixes #370 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #909 from zachjs/masterClifford Wolf2019-04-221-1/+20
|\ | | | | support repeat loops with constant repeat counts outside of constant functions
| * support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-091-1/+20
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* | Add "noblackbox" attributeClifford Wolf2019-04-211-17/+27
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | New behavior for front-end handling of whiteboxesClifford Wolf2019-04-202-18/+70
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-182-4/+22
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix mem2reg handling of memories with upto data ports, fixes #888Clifford Wolf2019-03-211-1/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve "read_verilog -dump_vlog[12]" handling of upto rangesClifford Wolf2019-03-211-3/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve read_verilog debug output capabilitiesClifford Wolf2019-03-212-10/+18
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* fix local name resolution in prefix constructsZachary Snow2019-03-181-1/+5
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* Improve handling of "full_case" attributesClifford Wolf2019-03-141-0/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve handling of memories used in mem index expressions on LHS of an ↵Clifford Wolf2019-03-121-5/+16
| | | | | | assignment Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove outdated "blocking assignment to memory" warningClifford Wolf2019-03-121-10/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867Clifford Wolf2019-03-121-6/+8
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #858 from YosysHQ/clifford/svalabelsClifford Wolf2019-03-092-3/+10
|\ | | | | Add support for using SVA labels in yosys-smtbmc console output
| * Add support for SVA labels in read_verilogClifford Wolf2019-03-072-3/+10
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-15/+18
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #848 from YosysHQ/clifford/fix763Clifford Wolf2019-03-021-1/+5
|\ | | | | Fix error for wire decl in always block, fixes 763
| * Fix error for wire decl in always block, fixes #763Clifford Wolf2019-03-021-1/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-022-0/+20
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix $global_clock handling vs autowireClifford Wolf2019-03-021-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix $readmem[hb] for mem2reg memories, fixes #785Clifford Wolf2019-03-021-0/+35
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use mem2reg on memories that only have constant-index write portsClifford Wolf2019-03-012-0/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixes related to handling of autowires and upto-ranges, fixes #814Clifford Wolf2019-02-212-9/+12
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of expression width in $past, fixes #810Clifford Wolf2019-02-211-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix segfault in printing of some internal error messagesClifford Wolf2019-02-211-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-2/+2
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Fix segfault in AST simplifyClifford Wolf2018-12-181-0/+5
| | | | | | (as proposed by Dan Gisselquist) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make return value of $clog2 signedSylvain Munaut2018-11-241-1/+1
| | | | | | | | As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Various indenting fixes in AST front-end (mostly space vs tab issues)Clifford Wolf2018-11-043-99/+69
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make and dependent upon LSB onlyZipCPU2018-11-031-2/+8
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* Do not generate "reg assigned in a continuous assignment" warnings for "rand ↵Clifford Wolf2018-11-011-2/+15
| | | | | | reg" Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-203-134/+108
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* Support for SystemVerilog interfaces as a port in the top level module + ↵Ruben Undheim2018-10-201-3/+105
| | | | test case
* Fixed memory leakRuben Undheim2018-10-201-0/+1
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* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-184-14/+265
|\ | | | | Support for SystemVerilog interfaces and modports
| * Documentation improvements etc.Ruben Undheim2018-10-132-8/+35
| | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
| * Fix build error with clangRuben Undheim2018-10-121-1/+1
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| * Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-123-5/+68
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| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-124-14/+175
| | | | | | | | This time doing the changes mostly in AST before RTLIL generation
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