aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/ast
Commit message (Collapse)AuthorAgeFilesLines
...
* | Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-211-7/+11
|\ \ | | | | | | Improve specify parser
| * | verilog: fix $specify3 checkEddie Hung2020-02-131-7/+11
| | |
* | | Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-204-16/+221
|\ \ \ | |/ / |/| | Enum support
| * | remove unnecessary blank lineJeff Wang2020-02-171-2/+1
| | |
| * | add attributes for enumerated values in ilangJeff Wang2020-02-172-1/+68
| | | | | | | | | | | | | | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
| * | separate out enum_item/param implementation when they should be differentJeff Wang2020-02-171-7/+16
| | |
| * | fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6Jeff Wang2020-01-171-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | The if(str == node->str) is in fact necessary (otherwise causes generate for in Multiplier_2D in tests/simple/multiplier.v to fail with error message "Right hand side of 3rd expression of generate for-loop is not constant!"). Note: in PeterCrozier's implementation, the break only breaks out of the switch-case, not the outer for loop.
| * | fix enum in generate blocksJeff Wang2020-01-161-0/+20
| | |
| * | allow enums to be declared at toplevel scopeJeff Wang2020-01-161-0/+7
| | |
| * | partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-164-16/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* | | Modified $readmem[hb] to use '\' or '/' according the OSRodrigo Alejandro Melo2020-02-061-1/+6
| | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
* | | Merge branch 'master' of https://github.com/YosysHQ/yosysRodrigo Alejandro Melo2020-02-032-93/+110
|\ \ \ | | |/ | |/| | | | | | | | | | Solved a conflict into the CHANGELOG Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * | ast: Add support for $sformatf system functionDavid Shah2020-01-192-93/+110
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Replaced strlen by GetSize into simplify.ccRodrigo Alejandro Melo2020-02-031-2/+2
| | | | | | | | | | | | As recommended in CodingReadme. Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
* | Fixed a bug in the new feature of $readmem[hb] when an empty string is providedRodrigo Alejandro Melo2020-02-011-1/+1
| | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* | Modified the new search for files of $readmem[hb] to be backward compatibleRodrigo Alejandro Melo2020-01-311-3/+7
| | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* | $readmem[hb] file inclusion is now relative to the Verilog fileRodrigo Alejandro Melo2020-01-311-1/+2
|/ | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* Stray log_dumpEddie Hung2019-12-111-1/+0
|
* Preserve size of $genval$-s in for loopsEddie Hung2019-12-111-0/+17
|
* Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-144-9/+118
|\ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * frontends/ast: code styleDavid Shah2019-10-031-2/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Fix typedefs in blocksDavid Shah2019-10-031-2/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Add support for memories of a typedefDavid Shah2019-10-031-6/+20
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Add support for memory typedefsDavid Shah2019-10-031-2/+15
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Fix typedefs in packagesDavid Shah2019-10-031-4/+10
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Fix typedef parametersDavid Shah2019-10-031-2/+31
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-034-7/+55
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix for svinterfacesEddie Hung2019-09-301-2/+8
| |
* | module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-302-33/+51
|/
* Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵Clifford Wolf2019-09-202-18/+30
| | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of range selects on loop variables, fixes #1372Clifford Wolf2019-09-161-2/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1350 from YosysHQ/clifford/fixsby59Clifford Wolf2019-09-051-7/+18
|\ | | | | Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)"
| * Properly construct $live and $fair cells from "if (...) assume/assert ↵Clifford Wolf2019-09-021-7/+18
| | | | | | | | | | | | | | | | (s_eventually ...)" Fixes https://github.com/YosysHQ/SymbiYosys/issues/59 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Remove newlineEddie Hung2019-08-291-1/+0
| |
* | Restore non-deferred code, deferred case to ignore non constant attrEddie Hung2019-08-291-5/+12
| |
* | read_verilog -defer should still populate module attributesEddie Hung2019-08-281-5/+6
|/
* Do not propagate mem2reg attribute through to resultEddie Hung2019-08-221-1/+2
|
* mem2reg to preserve user attributes and srcEddie Hung2019-08-211-0/+4
|
* handle real values when deriving ast modulesJakob Wenzel2019-08-191-1/+4
|
* Revert "Merge pull request #1280 from ↵Eddie Hung2019-08-121-1/+1
| | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
* Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-101-1/+1
|
* Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-103-14/+14
|\ | | | | Cleanup a few barnacles across codebase
| * substr() -> compare()Eddie Hung2019-08-073-6/+6
| |
| * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-7/+7
| |
| * Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-071-15/+2
| |\
| * | IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
| | |
* | | Allow whitebox modules to be overwrittenEddie Hung2019-08-071-1/+1
| |/ |/|
* | Fix handling of functions/tasks without top-level begin-end block, fixes #1231Clifford Wolf2019-08-061-15/+2
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* initialize noblackbox and nowb in AstModule::cloneJakob Wenzel2019-07-221-0/+2
|
* genrtlil: emit \src attribute on CaseRule.whitequark2019-07-081-0/+1
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 08:48:36 +0000