iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	ast, rpc: record original name of $paramod\* as \hdlname attribute.	whitequark	2020-04-18	1	-0/+2
\| \| \| \| \| \| \| \| \| \|	The $paramod name mangling is not invertible (the \ character, which separates the module name from the parameters, is valid in the module name itself), which does not stop people from trying to invert it. This commit makes it easy to invert the name mangling by storing the original name explicitly, and fixes the firrtl backend to use the newly introduced attribute.
*	kernel: use more ID::*	Eddie Hung	2020-04-02	1	-1/+1
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*	kernel: more pass by const ref, more speedups	Eddie Hung	2020-03-18	1	-1/+1
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*	Fixes for MSVC build	Miodrag Milanovic	2019-10-04	1	-2/+6
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*	Define environ, fixes #1424	Miodrag Milanovic	2019-10-01	1	-0/+2
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*	rpc: new frontend.	whitequark	2019-09-30	1	-0/+589
	A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design.