| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | Verific: Produce errors for instantiating unknown module | Clifford Wolf | 2018-07-22 | 1 | -0/+3 | |
| |/ | | | | | | | | Because if the unknown module is connected to any constants, Verific will actually break all constants in the same module, even if they have nothing to do structurally with that instance of an unknown module. Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix verific -vlog-incdir and -vlog-libdir handling | Clifford Wolf | 2018-07-16 | 1 | -2/+13 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix "read -incdir" | Clifford Wolf | 2018-07-16 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "read -incdir" | Clifford Wolf | 2018-07-16 | 1 | -0/+19 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "verific -formal" and "read -formal" | Clifford Wolf | 2018-06-29 | 1 | -7/+15 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "read -sv -D" support | Clifford Wolf | 2018-06-28 | 1 | -2/+25 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "read -undef" | Clifford Wolf | 2018-06-28 | 1 | -0/+32 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add YOSYS_NOVERIFIC env variable for temporarily disabling verific | Clifford Wolf | 2018-06-22 | 1 | -22/+40 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add simplified "read" command, enable extnets in implicit Verific import | Clifford Wolf | 2018-06-21 | 1 | -0/+84 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add automatic verific import in hierarchy command | Clifford Wolf | 2018-06-20 | 1 | -0/+53 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add (* gclk *) attribute support | Clifford Wolf | 2018-06-01 | 1 | -0/+10 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add comment to VIPER #13453 work-around | Clifford Wolf | 2018-05-28 | 1 | -0/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix Verific handling of single-bit anyseq/anyconst wires | Clifford Wolf | 2018-05-25 | 1 | -2/+4 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE | Clifford Wolf | 2018-05-24 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix verific handling of anyconst/anyseq attributes | Clifford Wolf | 2018-05-24 | 1 | -15/+26 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix handling of anyconst/anyseq attrs in VHDL code via Verific | Clifford Wolf | 2018-05-15 | 1 | -6/+6 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add PRIM_HDL_ASSERTION support to Verific importer | Clifford Wolf | 2018-04-07 | 1 | -3/+19 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix handling of $global_clocking in Verific | Clifford Wolf | 2018-04-06 | 1 | -1/+7 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add Verific anyseq/anyconst/allseq/allconst attribute support | Clifford Wolf | 2018-04-06 | 1 | -2/+36 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "verific -autocover" | Clifford Wolf | 2018-04-06 | 1 | -4/+15 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Set RAM runtime flags for Verific frontend | makaimann | 2018-04-05 | 1 | -0/+3 | |
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| * | Fix handling of unclocked immediate assertions in Verific front-end | Clifford Wolf | 2018-03-26 | 1 | -1/+6 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Improve import of memories via Verific | Clifford Wolf | 2018-03-15 | 1 | -16/+23 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix handling of SV compilation units in Verific front-end | Clifford Wolf | 2018-03-14 | 1 | -28/+25 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Use Verific hier_tree component for elaboration | Clifford Wolf | 2018-03-08 | 1 | -0/+54 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix Verific handling of "assert property (..);" in always block | Clifford Wolf | 2018-03-07 | 1 | -4/+33 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "verific -import -V" | Clifford Wolf | 2018-03-07 | 1 | -4/+16 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Set Verific db_preserve_user_nets flag | Clifford Wolf | 2018-03-07 | 1 | -0/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add proper SVA seq.triggered support | Clifford Wolf | 2018-03-04 | 1 | -0/+7 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add VerificClocking class and refactor Verific DFF handling | Clifford Wolf | 2018-03-04 | 1 | -43/+158 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fixes and improvements in Verific SVA importer | Clifford Wolf | 2018-03-01 | 1 | -5/+9 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add $rose/$fell support to Verific bindings | Clifford Wolf | 2018-03-01 | 1 | -3/+22 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Continue refactoring of Verific SVA importer code | Clifford Wolf | 2018-02-28 | 1 | -62/+29 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add handling of verific OPER_REDUCE_NOR | Clifford Wolf | 2018-02-26 | 1 | -0/+6 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR | Clifford Wolf | 2018-02-26 | 1 | -0/+13 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX | Clifford Wolf | 2018-02-26 | 1 | -0/+25 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add support for SVA until statements via Verific | Clifford Wolf | 2018-02-18 | 1 | -23/+0 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Move Verific SVA importer to extra C++ source file | Clifford Wolf | 2018-02-18 | 1 | -1279/+905 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Merge Verific SVA preprocessor and SVA importer | Clifford Wolf | 2018-02-18 | 1 | -79/+44 | |
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| * | Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF | Clifford Wolf | 2018-02-15 | 1 | -1/+1 | |
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| * | Fix single-bit $stable handling in verific front-end | Clifford Wolf | 2018-02-01 | 1 | -0/+22 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add Verific attribute handling for assert/assume/cover/live/fair cells | Clifford Wolf | 2018-01-31 | 1 | -10/+16 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fixed handling of synchronous and asynchronous assertion/assumption/cover in ↵ | Clifford Wolf | 2018-01-23 | 1 | -27/+29 | |
| | | | | | | | verific bindings Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add support for Verific PRIM_SVA_NOT properties | Clifford Wolf | 2017-12-10 | 1 | -10/+25 | |
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| * | Add Verific OPER_SVA_STABLE support | Clifford Wolf | 2017-12-10 | 1 | -2/+32 | |
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| * | Refactoring Verific SVA rewriter | Clifford Wolf | 2017-12-10 | 1 | -62/+70 | |
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| * | Remove all PSL support code from verific.cc | Clifford Wolf | 2017-10-20 | 1 | -179/+17 | |
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| * | Add "verific -vlog-libdir" | Clifford Wolf | 2017-10-13 | 1 | -0/+12 | |
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| * | Add "verific -vlog-incdir" and "verific -vlog-define" | Clifford Wolf | 2017-10-13 | 1 | -0/+35 | |
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| * | Add Verific fairness/liveness support | Clifford Wolf | 2017-10-12 | 1 | -11/+32 | |
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index : iCE40/yosys | |
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