Commit message (Collapse) | Author | Age | Files | Lines | ||
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* | Update comment about supported SVA in verificsva.cc | Clifford Wolf | 2018-03-06 | 1 | -51/+8 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add SVA NON_CONSECUTIVE_REPEAT and GOTO_REPEAT support | Clifford Wolf | 2018-03-06 | 1 | -20/+41 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add SVA first_match() support | Clifford Wolf | 2018-03-06 | 1 | -0/+16 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add SVA within support | Clifford Wolf | 2018-03-06 | 1 | -2/+18 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add support for SVA sequence intersect | Clifford Wolf | 2018-03-06 | 1 | -36/+251 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add get_fsm_accept_reject for parsing SVA properties | Clifford Wolf | 2018-03-06 | 1 | -73/+86 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Simplified SVA "until" handling | Clifford Wolf | 2018-03-06 | 1 | -25/+16 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add proper SVA seq.triggered support | Clifford Wolf | 2018-03-04 | 3 | -37/+102 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add Verific SVA support for "seq and seq" expressions | Clifford Wolf | 2018-03-04 | 1 | -24/+94 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Refactor Verific SVA importer property parser | Clifford Wolf | 2018-03-04 | 1 | -56/+82 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add VerificClocking class and refactor Verific DFF handling | Clifford Wolf | 2018-03-04 | 3 | -126/+196 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add SVA support for sequence OR | Clifford Wolf | 2018-03-03 | 1 | -22/+33 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Fix handling of SVA "until seq.triggered" properties | Clifford Wolf | 2018-03-02 | 1 | -7/+25 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Update SVA cheat sheet in verificsva.cc | Clifford Wolf | 2018-03-02 | 1 | -2/+4 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Fix in Verific SVA importer handling of until_with | Clifford Wolf | 2018-03-01 | 1 | -7/+5 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Fixes and improvements in Verific SVA importer | Clifford Wolf | 2018-03-01 | 3 | -83/+136 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add $rose/$fell support to Verific bindings | Clifford Wolf | 2018-03-01 | 1 | -3/+22 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add support for PRIM_SVA_UNTIL to new SVA importer | Clifford Wolf | 2018-02-28 | 1 | -0/+27 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add DFSM generator to verific SVA importer | Clifford Wolf | 2018-02-28 | 1 | -19/+272 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Continue refactoring of Verific SVA importer code | Clifford Wolf | 2018-02-28 | 3 | -671/+172 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Major redesign of Verific SVA importer | Clifford Wolf | 2018-02-27 | 1 | -5/+573 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add handling of verific OPER_REDUCE_NOR | Clifford Wolf | 2018-02-26 | 1 | -0/+6 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR | Clifford Wolf | 2018-02-26 | 1 | -0/+13 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX | Clifford Wolf | 2018-02-26 | 1 | -0/+25 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add "SVA syntax cheat sheet" comment to verificsva.cc | Clifford Wolf | 2018-02-26 | 1 | -0/+34 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add Verific SVA support for ranges in repetition operator | Clifford Wolf | 2018-02-22 | 1 | -5/+26 | |
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* | Add support for SVA throughout via Verific | Clifford Wolf | 2018-02-21 | 1 | -2/+6 | |
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* | Add support for SVA sequence concatenation ranges via verific | Clifford Wolf | 2018-02-18 | 1 | -16/+124 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add support for SVA until statements via Verific | Clifford Wolf | 2018-02-18 | 2 | -34/+119 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Move Verific SVA importer to extra C++ source file | Clifford Wolf | 2018-02-18 | 4 | -1279/+1370 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Merge Verific SVA preprocessor and SVA importer | Clifford Wolf | 2018-02-18 | 1 | -79/+44 | |
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* | Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF | Clifford Wolf | 2018-02-15 | 1 | -1/+1 | |
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* | Fix single-bit $stable handling in verific front-end | Clifford Wolf | 2018-02-01 | 1 | -0/+22 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add Verific attribute handling for assert/assume/cover/live/fair cells | Clifford Wolf | 2018-01-31 | 1 | -10/+16 | |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Fix permissions on verific vdb files | Clifford Wolf | 2018-01-28 | 1 | -0/+1 | |
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* | Fixed handling of synchronous and asynchronous assertion/assumption/cover in ↵ | Clifford Wolf | 2018-01-23 | 1 | -27/+29 | |
| | | | | | | verific bindings Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | Add support for Verific PRIM_SVA_NOT properties | Clifford Wolf | 2017-12-10 | 1 | -10/+25 | |
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* | Add Verific OPER_SVA_STABLE support | Clifford Wolf | 2017-12-10 | 1 | -2/+32 | |
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* | Refactoring Verific SVA rewriter | Clifford Wolf | 2017-12-10 | 1 | -62/+70 | |
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* | Remove all PSL support code from verific.cc | Clifford Wolf | 2017-10-20 | 1 | -179/+17 | |
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* | Add "verific -vlog-libdir" | Clifford Wolf | 2017-10-13 | 1 | -0/+12 | |
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* | Add "verific -vlog-incdir" and "verific -vlog-define" | Clifford Wolf | 2017-10-13 | 1 | -0/+35 | |
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* | Update Verific README | Clifford Wolf | 2017-10-13 | 1 | -0/+7 | |
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* | Add Verific fairness/liveness support | Clifford Wolf | 2017-10-12 | 1 | -11/+32 | |
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* | Start work on pre-processor for Verific SVA properties | Clifford Wolf | 2017-10-10 | 1 | -10/+153 | |
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* | Improve handling of Verific errors | Clifford Wolf | 2017-10-05 | 1 | -11/+9 | |
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* | Improve Verific error handling, check VHDL static asserts | Clifford Wolf | 2017-10-04 | 1 | -11/+25 | |
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* | Fix nasty bug in Verific bindings | Clifford Wolf | 2017-10-04 | 1 | -1/+1 | |
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* | Add merging of "past FFs" to verific importer | Clifford Wolf | 2017-07-29 | 1 | -2/+76 | |
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* | Add minimal support for PSL in VHDL via Verific | Clifford Wolf | 2017-07-28 | 1 | -19/+155 | |
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