| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Read bigger Verilog files. | Kaj Tuomi | 2019-05-18 | 1 | -1/+1 |
| | | | | | Hit parser limit with 3M gate design. This commit fix it. | ||||
| * | Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 | Clifford Wolf | 2019-03-29 | 1 | -0/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "make coverage" | Clifford Wolf | 2018-08-27 | 1 | -4/+3 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Adjust makefiles to work with out-of-tree builds | Clifford Wolf | 2015-08-12 | 1 | -2/+4 |
| | | | | | This is based on work done by Larry Doolittle | ||||
| * | Enable bison to be customized | Fabio Utzig | 2015-01-08 | 1 | -1/+1 |
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| * | Updated lexers & parsers to include prefixes | William Speirs | 2014-10-15 | 1 | -12/+12 |
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| * | Added "make PRETTY=1" | Clifford Wolf | 2014-07-24 | 1 | -3/+3 |
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| * | Various improvements in support for generate statements | Clifford Wolf | 2013-12-04 | 1 | -1/+3 |
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| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+19 |
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index : iCE40/yosys | |
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