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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* preproc: Fix up conditional handling.Marcelina Kościelnicka2021-03-301-3/+17
| | | | | Fixes #2710. Fixes #2711.
* verilog: fix handling of nested ifdef directivesZachary Snow2021-03-011-11/+38
| | | | | - track depth so we know whether to consider higher-level elsifs - error on unmatched endif/elsif/else
* verilog: error on macro invocations with missing argument listsZachary Snow2021-02-191-1/+10
| | | | | | This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly use the arguments from the previous invocation.
* verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-281-1/+5
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* verilog: allow spaces in macro argumentsZachary Snow2021-01-201-1/+0
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* Fix SYNTHESIS always being defined in Verilog frontendgeorgerennie2020-12-011-1/+0
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* MSVC does not understand __builtin_unreachableAnonymous Maarten2020-06-171-1/+1
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* Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-271-132/+488
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-131-1/+1
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* Add check for valid macro names in macro definitionsClifford Wolf2019-11-071-7/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Support SystemVerilog `` extension for macrosJim Paris2018-05-171-1/+5
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* Skip spaces around macro argumentsJim Paris2018-05-171-0/+1
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* Add support for "yosys -E"Clifford Wolf2018-01-071-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Accommodate Windows-style paths during include-file processing.William D. Jones2017-11-141-4/+20
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* Minor coding style fixClifford Wolf2017-09-261-1/+1
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* Adding support for string macros and macros with arguments after includecombinatorylogic2017-09-211-41/+69
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* Add support for `resetall compiler directiveClifford Wolf2017-04-261-0/+7
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* Fix verilog pre-processor for multi-level relative includesClifford Wolf2017-03-141-4/+26
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* Added support for macros as include file namesClifford Wolf2016-11-281-0/+2
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* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-151-1/+14
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* SystemVerilog also has assume(), added implicit -D FORMALClifford Wolf2015-10-131-1/+2
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* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
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* Fixed handling of "//" in filenames in verilog pre-processorClifford Wolf2015-02-141-1/+1
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* Define YOSYS and SYNTHESIS in preprocClifford Wolf2015-01-021-1/+2
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* Re-introduced Yosys::readsome() helper functionClifford Wolf2014-10-231-5/+3
| | | | (f.read() + f.gcount() made problems with lines > 16kB)
* Replaced readsome() with read() and gcount()Clifford Wolf2014-10-151-3/+5
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* Fixed win32 troubles with f.readsome()Clifford Wolf2014-10-111-1/+1
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* Added format __attribute__ to stringf()Clifford Wolf2014-10-101-1/+1
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* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-231-15/+16
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* Fixed line numbers when using here-doc macrosClifford Wolf2014-08-141-4/+9
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* Added support for non-standard """ macro bodiesClifford Wolf2014-08-131-1/+12
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-0/+4
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* Fixed counting verilog line numbers for "// synopsys translate_off" sectionsClifford Wolf2014-07-301-1/+1
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* Fixed Verilog pre-processor for files with no trailing newlineClifford Wolf2014-07-291-1/+1
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* Using log_assert() instead of assert()Clifford Wolf2014-07-281-2/+1
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* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-171-1/+0
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* Fixed parsing of verilog macros at end of lineClifford Wolf2014-01-181-1/+1
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* Fixed parsing of non-arg macro calls followed by "("Clifford Wolf2013-12-271-1/+7
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* Fixed parsing of macros with no arguments and expansion text starting with "("Clifford Wolf2013-12-271-1/+2
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* Added elsif preproc supportClifford Wolf2013-12-181-1/+14
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* Added support for macro argumentsClifford Wolf2013-12-181-23/+75
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* Fixed O(n^2) performance bug in verilog preprocessorClifford Wolf2013-11-221-1/+1
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* Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵Clifford Wolf2013-11-221-11/+0
| | | | flex)
* Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-201-2/+12
| | | | 'read_verilog' command
* added option '-Dname[=definition]' to command 'read_verilog'Johann Glaser2013-05-191-2/+2
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* initial importClifford Wolf2013-01-051-0/+360
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