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* Merge pull request #2179 from splhack/static-castclairexen2020-07-011-0/+2
|\ | | | | Support SystemVerilog Static Cast
| * static cast: support changing size and signednessKazuki Sakamoto2020-06-191-0/+2
| | | | | | | | | | | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* | Support missing sub-assign and and-assign operatorsKamil Rakoczy2020-06-251-0/+2
| | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | Support missing xor-assign operatorLukasz Dalek2020-06-241-0/+1
| | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | Add plus-assignment operatorKamil Rakoczy2020-06-241-0/+1
| | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | Add or-assignment operatorKamil Rakoczy2020-06-241-0/+2
|/ | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Merge branch 'master' into structPeter Crozier2020-06-031-7/+8
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| * Merge pull request #2033 from boqwxp/cleanup-verilog-lexerwhitequark2020-05-291-6/+5
| |\ | | | | | | verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
| | * verilog: Move lexer location variables from global namespace to ↵Alberto Gonzalez2020-05-061-6/+5
| | | | | | | | | | | | `VERILOG_FRONTEND` namespace.
| * | Silence spurious warning in Verilog lexer when compiling with GCCRupert Swarbrick2020-05-261-1/+3
| |/ | | | | | | | | | | | | The chosen value shouldn't have any effect. I considered something clearly wrong like -1, but there's no checking inside the generated lexer, and I suspect this will cause even weirder bugs if triggered than just setting it to INITIAL.
* | Generalise structs and add support for packed unions.Peter Crozier2020-05-121-2/+4
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* | Implement SV structs.Peter Crozier2020-05-081-1/+6
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* Error duplicate declarations of a typedef name in the same scope.Peter Crozier2020-03-241-1/+1
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* Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-231-2/+15
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* Parser changes to support typedef.Peter2020-03-221-2/+26
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* refixed parsing of constant with comment between size and valueMarcus Comstedt2020-03-111-8/+23
| | | | | | The three parts of a based constant (size, base, digits) are now three separate tokens, allowing the linear whitespace (including comments) between them to be treated as normal inter-token whitespace.
* Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-19/+53
| | | | and RTLIL nodes.
* verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-131-1/+1
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* sv: Improve handling of wildcard port connectionsDavid Shah2020-02-021-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Add lexing and parsing of .* (wildcard port conns)David Shah2020-02-021-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-131-1/+1
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* sv: Correct parsing of always_comb, always_ff and always_latchDavid Shah2019-11-211-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix lexing of integer literals without radixClifford Wolf2019-09-131-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix lexing of integer literals, fixes #1364Clifford Wolf2019-09-121-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix read_verilog assert/assume/etc on default case label, fixes ↵Clifford Wolf2019-07-021-0/+2
| | | | | | YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-111-1/+1
| | | | (within always/initial blocks)
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-071-0/+5
|\ | | | | | | clifford/pr983
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-0/+5
| | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | Merge branch 'master' into wandworStefan Biereigel2019-05-271-1/+1
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| * | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-271-1/+1
| | | | | | | | | | | | Includes work from @sumit0190 and @AaronKel
* | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-231-0/+2
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* | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-061-0/+2
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| * \ Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-041-0/+1
| |\ \ | | | | | | | | Add approximate support for SV "var" keyword
| | * | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-041-0/+1
| | |/ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * / Add support for SVA "final" keywordClifford Wolf2019-05-041-0/+1
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve $specrule interfaceClifford Wolf2019-04-231-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add specify parserClifford Wolf2019-04-231-1/+6
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-101-49/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Also add support for labels on sva module items, fixes #699Clifford Wolf2019-03-081-5/+52
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-181-0/+8
|\ | | | | Support for SystemVerilog interfaces and modports
| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+8
| | | | | | | | This time doing the changes mostly in AST before RTLIL generation
* | ignore protect endprotectargama2018-10-161-0/+3
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* Add "make coverage"Clifford Wolf2018-08-271-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-151-1/+1
|\ | | | | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
| * This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
* | Support more character literalsDan Gisselquist2018-05-031-1/+9
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