| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -1/+5 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) | |||||
| * | | Detect illegal port declaration, e.g input/output/inout keyword must be the ↵ | Udi Finkelstein | 2018-06-06 | 1 | -3/+6 | |
| | | | | | | | | | first. | |||||
| * | | Add statement labels for immediate assertions | Clifford Wolf | 2018-04-13 | 1 | -18/+21 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Allow "property" in immediate assertions | Clifford Wolf | 2018-04-12 | 1 | -17/+20 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add read_verilog anyseq/anyconst/allseq/allconst attribute support | Clifford Wolf | 2018-04-06 | 1 | -1/+33 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | First draft of Verilog parser support for specify blocks and parameters. | Udi Finkelstein | 2018-03-27 | 1 | -2/+167 | |
| |/ | | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST | |||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -1/+3 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add Verilog "automatic" keyword (ignored in synthesis) | Clifford Wolf | 2017-11-23 | 1 | -13/+17 | |
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| * | Accept real-valued delay values | Clifford Wolf | 2017-11-18 | 1 | -0/+1 | |
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| * | Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the ↵ | Udi Finkelstein | 2017-09-30 | 1 | -3/+5 | |
| | | | | | | | textbook solution (Oreilly 'Flex & Bison' page 189) | |||||
| * | Fix ignoring of simulation timings so that invalid module parameters cause ↵ | Clifford Wolf | 2017-09-26 | 1 | -0/+2 | |
| | | | | | syntax errors | |||||
| * | Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵ | Clifford Wolf | 2017-06-07 | 1 | -0/+1 | |
| | | | | | const reg" | |||||
| * | Fix handling of Verilog ~& and ~| operators | Clifford Wolf | 2017-06-01 | 1 | -0/+8 | |
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| * | Add support for localparam in module header | Clifford Wolf | 2017-04-30 | 1 | -1/+7 | |
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| * | Allow $anyconst, etc. in non-formal SV mode | Clifford Wolf | 2017-03-01 | 1 | -1/+1 | |
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| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -1/+25 | |
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| * | Add support for SystemVerilog unique, unique0, and priority case | Clifford Wolf | 2017-02-23 | 1 | -4/+21 | |
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| * | Added SystemVerilog support for ++ and -- | Clifford Wolf | 2017-02-23 | 1 | -0/+9 | |
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| * | Add checker support to verilog front-end | Clifford Wolf | 2017-02-09 | 1 | -2/+13 | |
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| * | Add SV "rand" and "const rand" support | Clifford Wolf | 2017-02-08 | 1 | -6/+24 | |
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| * | Further improve cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+6 | |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -1/+7 | |
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| * | Add "enum" and "typedef" lexer support | Clifford Wolf | 2017-01-17 | 1 | -1/+1 | |
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| * | Added support for hierarchical defparams | Clifford Wolf | 2016-11-15 | 1 | -3/+2 | |
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| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 1 | -1/+1 | |
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| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 1 | -1/+1 | |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -7/+1 | |
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| * | Added read_verilog -norestrict -assume-asserts | Clifford Wolf | 2016-08-26 | 1 | -3/+16 | |
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| * | Improved verilog parser errors | Clifford Wolf | 2016-08-25 | 1 | -0/+3 | |
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| * | Fixed bug in parsing real constants | Clifford Wolf | 2016-08-06 | 1 | -4/+4 | |
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| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 1 | -1/+1 | |
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| * | Fixed a verilog parser memory leak | Clifford Wolf | 2016-07-25 | 1 | -0/+1 | |
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| * | Fixed parsing of empty positional cell ports | Clifford Wolf | 2016-07-25 | 1 | -2/+31 | |
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| * | No tristate warning message for "read_verilog -lib" | Clifford Wolf | 2016-07-23 | 1 | -5/+5 | |
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| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 1 | -0/+2 | |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -5/+5 | |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -1/+8 | |
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| * | Allow defining input ports as "input logic" in SystemVerilog | Ruben Undheim | 2016-06-20 | 1 | -2/+2 | |
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| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 1 | -0/+29 | |
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| * | Fixed handling of parameters and const functions in casex/casez pattern | Clifford Wolf | 2016-04-21 | 1 | -2/+6 | |
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| * | Fixed Verilog parser fix and more similar improvements | Clifford Wolf | 2016-03-15 | 1 | -18/+9 | |
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| * | Use left-recursive rule for cell_port_list in Verilog parser. | Andrew Becker | 2016-03-15 | 1 | -6/+10 | |
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| * | Fixed handling of parameters and localparams in functions | Clifford Wolf | 2015-11-11 | 1 | -1/+1 | |
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| * | Fixed bug in verilog parser | Clifford Wolf | 2015-10-15 | 1 | -1/+1 | |
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| * | Added support for "parameter" and "localparam" in global context | Clifford Wolf | 2015-10-07 | 1 | -0/+2 | |
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| * | Fixed detection of "task foo(bar);" syntax error | Clifford Wolf | 2015-09-22 | 1 | -0/+2 | |
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| * | Adjust makefiles to work with out-of-tree builds | Clifford Wolf | 2015-08-12 | 1 | -1/+1 | |
| | | | | | This is based on work done by Larry Doolittle | |||||
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -5/+5 | |
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| * | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 | 1 | -2/+8 | |
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| * | Parser support for complex delay expressions | Clifford Wolf | 2015-02-20 | 1 | -7/+20 | |
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index : iCE40/yosys | |
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