| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Merge pull request #2179 from splhack/static-cast | clairexen | 2020-07-01 | 1 | -0/+19 | |
| |\ \ | | | | | | | Support SystemVerilog Static Cast | |||||
| | * | | static cast: support changing size and signedness | Kazuki Sakamoto | 2020-06-19 | 1 | -0/+19 | |
| | |/ | | | | | | | | | | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535 | |||||
| * | | Merge pull request #2188 from antmicro/missing-operators | whitequark | 2020-06-26 | 1 | -2/+43 | |
| |\ \ | | | | | | | Add logic-assignments operators | |||||
| | * | | Support missing sub-assign and and-assign operators | Kamil Rakoczy | 2020-06-25 | 1 | -2/+19 | |
| | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | |||||
| | * | | Support missing xor-assign operator | Lukasz Dalek | 2020-06-24 | 1 | -1/+9 | |
| | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> | |||||
| | * | | Add plus-assignment operator | Kamil Rakoczy | 2020-06-24 | 1 | -1/+9 | |
| | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | |||||
| | * | | Add or-assignment operator | Kamil Rakoczy | 2020-06-24 | 1 | -1/+9 | |
| | |/ | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | |||||
| * | | Support optional labels at the end of package definition | Lukasz Dalek | 2020-06-24 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> | |||||
| * | | Support optional labels at the end of module definition | Lukasz Dalek | 2020-06-24 | 1 | -1/+1 | |
| |/ | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> | |||||
| * | MSVC cannot omit operand in conditional | Anonymous Maarten | 2020-06-17 | 1 | -1/+1 | |
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| * | Support packed arrays in struct/union. | Peter Crozier | 2020-06-07 | 1 | -5/+5 | |
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| * | Merge branch 'master' into struct | Peter Crozier | 2020-06-03 | 1 | -31/+48 | |
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| | * | verilog: move attr from simple_behav_stmt to its children to attach | Eddie Hung | 2020-05-25 | 1 | -13/+17 | |
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| | * | verilog: do not warn for attributes on null statements | Eddie Hung | 2020-05-25 | 1 | -2/+0 | |
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| | * | verilog: handle empty generate statement by removing gen_stmt_or_null... | Eddie Hung | 2020-05-25 | 1 | -7/+8 | |
| | | | | | | | | | | | ... rule which causes a s/r conflict. Now we get an empty genblock, which should be okay. | |||||
| | * | verilog: fix #2037 by permitting (and freeing) attributes on null stmt | Eddie Hung | 2020-05-25 | 1 | -1/+5 | |
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| | * | Merge pull request #2057 from YosysHQ/eddie/fix_task_attr | Eddie Hung | 2020-05-21 | 1 | -11/+9 | |
| | |\ | | | | | | | verilog: support attributes before (not after) task identifier (but 13 s/r conflicts) | |||||
| | | * | Update frontends/verilog/verilog_parser.y | Eddie Hung | 2020-05-21 | 1 | -1/+1 | |
| | | | | | | | | | | Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com> | |||||
| | | * | verilog: attributes before task enable (but 13 s/r conflicts) | Eddie Hung | 2020-05-14 | 1 | -10/+8 | |
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| | * | | verilog: default to input in sv mode if task/func has no dir ... | Eddie Hung | 2020-05-13 | 1 | -2/+10 | |
| | | | | | | | | | | | | | otherwise error | |||||
| | * | | verilog: error out when non-ANSI task/func arguments | Eddie Hung | 2020-05-11 | 1 | -1/+5 | |
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| * | | Allow structs within structs. | Peter Crozier | 2020-05-12 | 1 | -7/+18 | |
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| * | | Generalise structs and add support for packed unions. | Peter Crozier | 2020-05-12 | 1 | -16/+34 | |
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| * | | Implement SV structs. | Peter Crozier | 2020-05-08 | 1 | -101/+180 | |
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| * | Merge pull request #2005 from YosysHQ/claire/fix1990 | Claire Wolf | 2020-05-07 | 1 | -2/+2 | |
| |\ | | | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset | |||||
| | * | Add AST_SELFSZ and improve handling of bit slices | Claire Wolf | 2020-05-02 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
| * | | Merge pull request #2028 from zachjs/master | Eddie Hung | 2020-05-06 | 1 | -1/+6 | |
| |\ \ | | | | | | | verilog: allow null gen-if then block | |||||
| | * | | verilog: allow null gen-if then block | Zachary Snow | 2020-05-06 | 1 | -1/+6 | |
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| * | | Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup | Eddie Hung | 2020-05-05 | 1 | -13/+13 | |
| |\ \ | | | | | | | frontend: cleanup to use more ID::*, more dict<> instead of map<> | |||||
| | * | | frontend: cleanup to use more ID::*, more dict<> instead of map<> | Eddie Hung | 2020-05-04 | 1 | -13/+13 | |
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| * | | Merge pull request #2024 from YosysHQ/eddie/primitive_src | Eddie Hung | 2020-05-05 | 1 | -1/+3 | |
| |\ \ | | | | | | | verilog: set src attribute for primitives | |||||
| | * | | verilog: set src attribute for primitives | Eddie Hung | 2020-05-04 | 1 | -1/+3 | |
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| * / | verilog: fix specify src attribute | Eddie Hung | 2020-05-04 | 1 | -18/+20 | |
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| * | Set Verilog source location for explicit blocks (`begin` ... `end`). | Alberto Gonzalez | 2020-04-17 | 1 | -0/+1 | |
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| * | Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` ↵ | Alberto Gonzalez | 2020-04-17 | 1 | -0/+2 | |
| | | | | | nodes. | |||||
| * | Add location information to `AST_CONSTANT` nodes. | Alberto Gonzalez | 2020-04-16 | 1 | -0/+3 | |
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| * | Merge pull request #1879 from jjj11x/jjj11x/package_decl | whitequark | 2020-04-14 | 1 | -1/+2 | |
| |\ | | | | | support using previously declared types/localparams/parameters in package | |||||
| | * | support using previously declared types/localparams/params in package | Jeff Wang | 2020-04-07 | 1 | -1/+2 | |
| | | | | | | | | | | | | | | | (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also) | |||||
| * | | verilog: Fix write to deleted object | David Shah | 2020-04-12 | 1 | -1/+0 | |
| |/ | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -5/+5 | |
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| * | kernel: use more ID::* | Eddie Hung | 2020-04-02 | 1 | -22/+22 | |
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| * | verilog: Add location info for generate constructs | David Shah | 2020-04-01 | 1 | -0/+6 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | Inline productions to follow house style. | Peter Crozier | 2020-03-27 | 1 | -33/+29 | |
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| * | Error duplicate declarations of a typedef name in the same scope. | Peter Crozier | 2020-03-24 | 1 | -2/+10 | |
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| * | Support module/package/interface/block scope for typedef names. | Peter Crozier | 2020-03-23 | 1 | -15/+36 | |
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| * | Clear pkg_user_types if no packages following a 'design -reset-vlog'. | Peter | 2020-03-22 | 1 | -0/+1 | |
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| * | Parser changes to support typedef. | Peter | 2020-03-22 | 1 | -8/+37 | |
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| * | Merge pull request #1775 from huaixv/asserts_locations | N. Engelhardt | 2020-03-19 | 1 | -7/+30 | |
| |\ | | | | | Add precise locations for asserts | |||||
| | * | Add precise locations for asserts | huaixv | 2020-03-19 | 1 | -7/+30 | |
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| * | | Add AST node source location information in a couple more parser rules. | Alberto Gonzalez | 2020-03-17 | 1 | -0/+2 | |
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