| Commit message (Expand) | Author | Age | Files | Lines |
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| * | | Merge pull request #946 from YosysHQ/clifford/specify | Clifford Wolf | 2019-05-06 | 1 | -22/+295 |
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| | * \ | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify | Clifford Wolf | 2019-05-06 | 1 | -2/+8 |
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| | * | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -8/+18 |
| | * | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -20/+18 |
| | * | | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -2/+67 |
| | * | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| | * | | | Add specify parser | Clifford Wolf | 2019-04-23 | 1 | -22/+222 |
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| * | | | verilog_parser: Fix Bison warning | Ben Widawsky | 2019-05-05 | 1 | -1/+1 |
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| * | | Merge pull request #988 from YosysHQ/clifford/fix987 | Clifford Wolf | 2019-05-04 | 1 | -1/+4 |
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| | * | | Add approximate support for SV "var" keyword, fixes #987 | Clifford Wolf | 2019-05-04 | 1 | -1/+4 |
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| * / | Add support for SVA "final" keyword | Clifford Wolf | 2019-05-04 | 1 | -1/+4 |
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| * | New behavior for front-end handling of whiteboxes | Clifford Wolf | 2019-04-20 | 1 | -5/+5 |
| * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -5/+5 |
| * | Fix handling of cases that look like sva labels, fixes #862 | Clifford Wolf | 2019-03-10 | 1 | -43/+56 |
| * | Also add support for labels on sva module items, fixes #699 | Clifford Wolf | 2019-03-08 | 1 | -39/+61 |
| * | Add support for SVA labels in read_verilog | Clifford Wolf | 2019-03-07 | 1 | -23/+79 |
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -3/+3 |
| * | verilog_parser: Properly handle recursion when processing attributes | Sylvain Munaut | 2018-12-14 | 1 | -19/+29 |
| * | Add warning for SV "restrict" without "property" | Clifford Wolf | 2018-11-04 | 1 | -2/+11 |
| * | Fix minor typo in error message | Clifford Wolf | 2018-10-25 | 1 | -1/+1 |
| * | Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars... | Udi Finkelstein | 2018-10-25 | 1 | -14/+14 |
| * | Handle FIXME for modport members without type directly in front | Ruben Undheim | 2018-10-13 | 1 | -6/+8 |
| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -3/+21 |
| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+60 |
| * | Add "read_verilog -noassert -noassume -assert-assumes" | Clifford Wolf | 2018-09-24 | 1 | -5/+18 |
| * | Added support for ommited "parameter" in Verilog-2001 style parameter decl in... | Clifford Wolf | 2018-09-23 | 1 | -3/+9 |
| * | Fixed all known specify/endspecify issues, without breaking 'make test'. | Udi Finkelstein | 2018-08-20 | 1 | -12/+12 |
| * | Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout... | Udi Finkelstein | 2018-08-20 | 1 | -10/+22 |
| * | A few minor enhancements to specify block parsing. | Udi Finkelstein | 2018-08-15 | 1 | -2/+13 |
| * | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 1 | -1/+6 |
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| | * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -0/+1 |
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -1/+5 |
| * | | Detect illegal port declaration, e.g input/output/inout keyword must be the f... | Udi Finkelstein | 2018-06-06 | 1 | -3/+6 |
| * | | Add statement labels for immediate assertions | Clifford Wolf | 2018-04-13 | 1 | -18/+21 |
| * | | Allow "property" in immediate assertions | Clifford Wolf | 2018-04-12 | 1 | -17/+20 |
| * | | Add read_verilog anyseq/anyconst/allseq/allconst attribute support | Clifford Wolf | 2018-04-06 | 1 | -1/+33 |
| * | | First draft of Verilog parser support for specify blocks and parameters. | Udi Finkelstein | 2018-03-27 | 1 | -2/+167 |
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| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -1/+3 |
| * | Add Verilog "automatic" keyword (ignored in synthesis) | Clifford Wolf | 2017-11-23 | 1 | -13/+17 |
| * | Accept real-valued delay values | Clifford Wolf | 2017-11-18 | 1 | -0/+1 |
| * | Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textboo... | Udi Finkelstein | 2017-09-30 | 1 | -3/+5 |
| * | Fix ignoring of simulation timings so that invalid module parameters cause sy... | Clifford Wolf | 2017-09-26 | 1 | -0/+2 |
| * | Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand cons... | Clifford Wolf | 2017-06-07 | 1 | -0/+1 |
| * | Fix handling of Verilog ~& and ~| operators | Clifford Wolf | 2017-06-01 | 1 | -0/+8 |
| * | Add support for localparam in module header | Clifford Wolf | 2017-04-30 | 1 | -1/+7 |
| * | Allow $anyconst, etc. in non-formal SV mode | Clifford Wolf | 2017-03-01 | 1 | -1/+1 |
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -1/+25 |
| * | Add support for SystemVerilog unique, unique0, and priority case | Clifford Wolf | 2017-02-23 | 1 | -4/+21 |
| * | Added SystemVerilog support for ++ and -- | Clifford Wolf | 2017-02-23 | 1 | -0/+9 |
| * | Add checker support to verilog front-end | Clifford Wolf | 2017-02-09 | 1 | -2/+13 |
