iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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* \|	fix indentation across files	Stefan Biereigel	2019-05-23	1	-2/+2
* \|	make lexer/parser aware of wand/wor net types	Stefan Biereigel	2019-05-23	1	-1/+7
* \|	Merge pull request #1013 from antmicro/parameter_attributes	Clifford Wolf	2019-05-16	1	-2/+2
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\| * \|	Added support for parsing attributes on parameters in Verilog frontent. Conte...	Maciej Kurc	2019-05-16	1	-2/+2
* \| \|	Make the generated *.tab.hh include all the headers needed to define the union.	Henner Zeller	2019-05-14	1	-1/+9
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* \|	Merge pull request #946 from YosysHQ/clifford/specify	Clifford Wolf	2019-05-06	1	-22/+295
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\| * \	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify	Clifford Wolf	+5
*	Fix ignoring of simulation timings so that invalid module parameters cause sy...	Clifford Wolf	2017-09-26	1	-0/+2
*	Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand cons...	Clifford Wolf	2017-06-07	1	-0/+1
*	Fix handling of Verilog ~& and ~\| operators	Clifford Wolf	2017-06-01	1	-0/+8
*	Add support for localparam in module header	Clifford Wolf	2017-04-30	1	-1/+7