Commit message (Collapse) | Author | Age | Files | Lines | ||
---|---|---|---|---|---|---|
... | ||||||
* | YosysJS stuff | Clifford Wolf | 2015-02-19 | 1 | -0/+1 | |
| | ||||||
* | Improved read_verilog support for empty behavioral statements | Clifford Wolf | 2015-02-10 | 1 | -6/+2 | |
| | ||||||
* | Fixed supply0/supply1 with many wires | Clifford Wolf | 2014-12-11 | 1 | -3/+15 | |
| | ||||||
* | Added warning for use of 'z' constants in HDL | Clifford Wolf | 2014-11-14 | 1 | -4/+4 | |
| | ||||||
* | Fixed parsing of nested verilog concatenation and replicate | Clifford Wolf | 2014-11-12 | 1 | -1/+1 | |
| | ||||||
* | Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..." | Clifford Wolf | 2014-10-30 | 1 | -4/+5 | |
| | ||||||
* | Added support for task and function args in parentheses | Clifford Wolf | 2014-10-27 | 1 | -6/+45 | |
| | ||||||
* | Updated lexers & parsers to include prefixes | William Speirs | 2014-10-15 | 1 | -0/+1434 | |