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* verilog: Add location info for generate constructsDavid Shah2020-04-011-0/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Inline productions to follow house style.Peter Crozier2020-03-271-33/+29
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* Error duplicate declarations of a typedef name in the same scope.Peter Crozier2020-03-241-2/+10
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* Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-231-15/+36
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* Clear pkg_user_types if no packages following a 'design -reset-vlog'.Peter2020-03-221-0/+1
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* Parser changes to support typedef.Peter2020-03-221-8/+37
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* Merge pull request #1775 from huaixv/asserts_locationsN. Engelhardt2020-03-191-7/+30
|\ | | | | Add precise locations for asserts
| * Add precise locations for assertshuaixv2020-03-191-7/+30
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* | Add AST node source location information in a couple more parser rules.Alberto Gonzalez2020-03-171-0/+2
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* Merge pull request #1759 from zeldin/constant_with_comment_reduxMiodrag Milanović2020-03-141-11/+20
|\ | | | | refixed parsing of constant with comment between size and value
| * refixed parsing of constant with comment between size and valueMarcus Comstedt2020-03-111-11/+20
| | | | | | | | | | | | The three parts of a based constant (size, base, digits) are now three separate tokens, allowing the linear whitespace (including comments) between them to be treated as normal inter-token whitespace.
* | verilog: also set location for simple_behavioral_stmtEddie Hung2020-03-101-0/+4
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* | Set AST source locations in more parser rules.Alberto Gonzalez2020-03-101-2/+49
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* Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-081-4/+6
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Fix bison warning for "pure-parser" optionClaire Wolf2020-03-031-1/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-11/+77
| | | | and RTLIL nodes.
* Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-211-28/+80
|\ | | | | Improve specify parser
| * verilog: add support for more delays than just rise/fallEddie Hung2020-02-191-1/+40
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| * verilog: ignore ranges too without -specifyEddie Hung2020-02-131-1/+2
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| * verilog: improve specify support when not in -specify modeEddie Hung2020-02-131-13/+7
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| * verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-131-4/+5
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| * specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-12/+29
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* | Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-201-2/+104
|\ \ | |/ |/| Enum support
| * add attributes for enumerated values in ilangJeff Wang2020-02-171-1/+8
| | | | | | | | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
| * lexer doesn't seem to return TOK_REG for logic anymoreJeff Wang2020-01-161-3/+4
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| * allow enum typedefsJeff Wang2020-01-161-1/+6
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| * partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-161-1/+90
| | | | | | | | | | | | | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-131-2/+2
|\ \ | | | | | | Fix crash on wire declaration with delay
| * | correct wire declaration grammar for #1614Stefan Biereigel2020-02-031-2/+2
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* | sv: Improve handling of wildcard port connectionsDavid Shah2020-02-021-3/+5
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-021-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | sv: Add lexing and parsing of .* (wildcard port conns)David Shah2020-02-021-1/+4
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-041-5/+5
| | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs.
* sv: Correct parsing of always_comb, always_ff and always_latchDavid Shah2019-11-211-2/+37
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-141-11/+69
|\ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * sv: Disambiguate interface portsDavid Shah2019-10-031-3/+19
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Fix memories of typedefsDavid Shah2019-10-031-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Add %expectDavid Shah2019-10-031-0/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Add support for memory typedefsDavid Shah2019-10-031-1/+19
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Fix typedef parametersDavid Shah2019-10-031-4/+17
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-4/+34
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* substr() -> compare()Eddie Hung2019-08-071-4/+4
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* Some cleanups in "ignore specify parser"Clifford Wolf2019-07-031-79/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve specify dummy parser, fixes #1144Clifford Wolf2019-06-281-2/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make genvar a signed typeEddie Hung2019-06-201-0/+1
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* Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵Clifford Wolf2019-06-201-1/+7
|\ | | | | | | towoe-unpacked_arrays
| * Unpacked array declaration using sizeTobias Wölfel2019-06-191-1/+7
| | | | | | | | | | | | | | | | Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work.
* | Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-191-2/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add defaultvalue attributeClifford Wolf2019-06-191-0/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix handling of "logic" variables with initial valueClifford Wolf2019-06-191-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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