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* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-071-1/+10
|\ | | | | | | clifford/pr983
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-1/+10
| | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-071-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-071-1/+10
|\ \ | | | | | | | | | into tux3-implicit_named_connection
| * | SystemVerilog support for implicit named port connectionstux32019-06-061-9/+17
| | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
* | | Fixed memory leak.Maciej Kurc2019-06-051-0/+4
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
|/ / | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | fix indentation across filesStefan Biereigel2019-05-231-2/+2
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* | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-231-1/+7
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* | Merge pull request #1013 from antmicro/parameter_attributesClifford Wolf2019-05-161-2/+2
|\ \ | | | | | | Support for attributes on parameters and localparams for Verilog frontend
| * | Added support for parsing attributes on parameters in Verilog frontent. ↵Maciej Kurc2019-05-161-2/+2
| | | | | | | | | | | | | | | | | | Content of those attributes is ignored. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-141-1/+9
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* | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-061-22/+295
|\ \ | | | | | | Add specify parser
| * \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-061-2/+8
| |\ \
| * | | Improve $specrule interfaceClifford Wolf2019-04-231-8/+18
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Improve $specrule interfaceClifford Wolf2019-04-231-20/+18
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-2/+67
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add specify parserClifford Wolf2019-04-231-22/+222
| | |/ | |/| | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | verilog_parser: Fix Bison warningBen Widawsky2019-05-051-1/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | As of Bison 2.6, name-prefix is deprecated. This fixes frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated] %name-prefix "frontend_verilog_yy" For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html Compile tested only. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* | Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-041-1/+4
|\ \ | | | | | | Add approximate support for SV "var" keyword
| * | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-041-1/+4
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / Add support for SVA "final" keywordClifford Wolf2019-05-041-1/+4
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* New behavior for front-end handling of whiteboxesClifford Wolf2019-04-201-5/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-5/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-101-43/+56
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Also add support for labels on sva module items, fixes #699Clifford Wolf2019-03-081-39/+61
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for SVA labels in read_verilogClifford Wolf2019-03-071-23/+79
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-3/+3
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
| | | | | | Fixes #737 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵Udi Finkelstein2018-10-251-14/+14
| | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
* Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
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* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+21
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* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+60
| | | | This time doing the changes mostly in AST before RTLIL generation
* Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-09-241-5/+18
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Added support for ommited "parameter" in Verilog-2001 style parameter decl ↵Clifford Wolf2018-09-231-3/+9
| | | | | | in SV mode Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixed all known specify/endspecify issues, without breaking 'make test'.Udi Finkelstein2018-08-201-12/+12
| | | | | Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts, due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
* Yosys can now parse ↵Udi Finkelstein2018-08-201-10/+22
| | | | | | | https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , (specify block ignored). Must use 'read_verilog -defer' due to a parameter not assigned a default value.
* A few minor enhancements to specify block parsing.Udi Finkelstein2018-08-151-2/+13
| | | | Just remember specify blocks are parsed but ignored.
* Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-151-1/+6
|\ | | | | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
| * Modified errors into warningsUdi Finkelstein2018-06-051-0/+1
| | | | | | | | No longer false warnings for memories and assertions
| * This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-111-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
* | Detect illegal port declaration, e.g input/output/inout keyword must be the ↵Udi Finkelstein2018-06-061-3/+6
| | | | | | | | first.
* | Add statement labels for immediate assertionsClifford Wolf2018-04-131-18/+21
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Allow "property" in immediate assertionsClifford Wolf2018-04-121-17/+20
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add read_verilog anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-1/+33
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-271-2/+167
|/ | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 06:46:42 +0000