iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12	3	-4/+6
\| \| \| \|	This is based on work done by Larry Doolittle
*	Fixed handling of [a-fxz?] in decimal constants	Clifford Wolf	2015-08-11	1	-2/+7
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*	Add -noautowire option to verilog frontend	Marcus Comstedt	2015-08-01	1	-1/+8
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	6	-16/+16
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*	Verilog front-end: define `BLACKBOX in -lib mode	Clifford Wolf	2015-04-19	1	-1/+2
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*	Ignore celldefine directive in verilog front-end	Clifford Wolf	2015-03-25	1	-0/+3
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*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26	4	-5/+25
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*	Parser support for complex delay expressions	Clifford Wolf	2015-02-20	1	-7/+20
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*	YosysJS stuff	Clifford Wolf	2015-02-19	1	-0/+1
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*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14	1	-1/+15
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*	Fixed handling of "//" in filenames in verilog pre-processor	Clifford Wolf	2015-02-14	2	-1/+5
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*	Improved read_verilog support for empty behavioral statements	Clifford Wolf	2015-02-10	1	-6/+2
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*	Ignoring more system task and functions	Clifford Wolf	2015-01-15	1	-1/+1
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*	Enable bison to be customized	Fabio Utzig	2015-01-08	1	-1/+1
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*	Define YOSYS and SYNTHESIS in preproc	Clifford Wolf	2015-01-02	1	-1/+2
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*	Improved some warning messages	Clifford Wolf	2014-12-27	1	-6/+18
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*	Fixed supply0/supply1 with many wires	Clifford Wolf	2014-12-11	1	-3/+15
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*	Fixed minor bug in parsing delays	Clifford Wolf	2014-11-24	1	-1/+4
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*	Fixed two minor bugs in constant parsing	Clifford Wolf	2014-11-24	2	-3/+7
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*	Added warning for use of 'z' constants in HDL	Clifford Wolf	2014-11-14	3	-6/+14
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*	Fixed parsing of nested verilog concatenation and replicate	Clifford Wolf	2014-11-12	1	-1/+1
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*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-6/+6
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*	Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."	Clifford Wolf	2014-10-30	1	-4/+5
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*	Added support for task and function args in parentheses	Clifford Wolf	2014-10-27	1	-6/+45
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*	Re-introduced Yosys::readsome() helper function	Clifford Wolf	2014-10-23	2	-10/+4
\| \| \| \|	(f.read() + f.gcount() made problems with lines > 16kB)
*	Print "SystemVerilog" in "read_verilog -sv" log messages	Clifford Wolf	2014-10-16	1	-1/+1
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*	Updated .gitignore file for ilang and verilog frontends	Clifford Wolf	2014-10-15	1	-4/+4
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*	Replaced readsome() with read() and gcount()	Clifford Wolf	2014-10-15	1	-3/+5
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*	Updated lexers & parsers to include prefixes	William Speirs	2014-10-15	3	-14/+18
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*	Fixed win32 troubles with f.readsome()	Clifford Wolf	2014-10-11	2	-2/+2
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*	Added format __attribute__ to stringf()	Clifford Wolf	2014-10-10	1	-1/+1
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*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-1/+1
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*	namespace Yosys	Clifford Wolf	2014-09-27	1	-16/+16
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*	Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore	Clifford Wolf	2014-08-23	1	-4/+1
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*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	5	-22/+30
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*	Added support for non-standard <plugin>:<c_name> DPI syntax	Clifford Wolf	2014-08-22	1	-0/+12
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*	Added support for DPI function with different names in C and Verilog	Clifford Wolf	2014-08-21	2	-5/+16
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*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21	2	-1/+54
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*	Added support for global tasks and functions	Clifford Wolf	2014-08-21	2	-15/+23
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*	Added "via_celltype" attribute on task/func	Clifford Wolf	2014-08-18	1	-12/+14
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*	Fixed line numbers when using here-doc macros	Clifford Wolf	2014-08-14	1	-4/+9
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*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13	1	-1/+12
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*	Also allow "module foobar(input foo, output bar, ...);" syntax	Clifford Wolf	2014-08-07	1	-3/+5
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*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06	1	-4/+18
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*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05	1	-2/+1
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*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04	1	-1/+7
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	6	-3/+24
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*	Fixed counting verilog line numbers for "// synopsys translate_off" sections	Clifford Wolf	2014-07-30	2	-4/+4
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*	Fixed Verilog pre-processor for files with no trailing newline	Clifford Wolf	2014-07-29	1	-1/+1
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	3	-5/+2
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