| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Fix minor typo in error message | Clifford Wolf | 2018-10-25 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵ | Udi Finkelstein | 2018-10-25 | 1 | -14/+14 | |
| | | | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages. | |||||
| * | Merge pull request #659 from rubund/sv_interfaces | Clifford Wolf | 2018-10-18 | 2 | -0/+88 | |
| |\ | | | | | Support for SystemVerilog interfaces and modports | |||||
| | * | Handle FIXME for modport members without type directly in front | Ruben Undheim | 2018-10-13 | 1 | -6/+8 | |
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| | * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -3/+21 | |
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| | * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 2 | -0/+68 | |
| | | | | | | | | | This time doing the changes mostly in AST before RTLIL generation | |||||
| * | | ignore protect endprotect | argama | 2018-10-16 | 1 | -0/+3 | |
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| * | Add "read_verilog -noassert -noassume -assert-assumes" | Clifford Wolf | 2018-09-24 | 3 | -6/+49 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Added support for ommited "parameter" in Verilog-2001 style parameter decl ↵ | Clifford Wolf | 2018-09-23 | 1 | -3/+9 | |
| | | | | | | | in SV mode Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "make coverage" | Clifford Wolf | 2018-08-27 | 3 | -6/+5 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Merge pull request #610 from udif/udif_specify_round2 | Clifford Wolf | 2018-08-23 | 1 | -16/+39 | |
| |\ | | | | | More specify/endspecify fixes | |||||
| | * | Fixed all known specify/endspecify issues, without breaking 'make test'. | Udi Finkelstein | 2018-08-20 | 1 | -12/+12 | |
| | | | | | | | | | | | Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts, due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses | |||||
| | * | Yosys can now parse ↵ | Udi Finkelstein | 2018-08-20 | 1 | -10/+22 | |
| | | | | | | | | | | | | | | | https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , (specify block ignored). Must use 'read_verilog -defer' due to a parameter not assigned a default value. | |||||
| | * | A few minor enhancements to specify block parsing. | Udi Finkelstein | 2018-08-15 | 1 | -2/+13 | |
| | | | | | | | | | Just remember specify blocks are parsed but ignored. | |||||
| * | | Added -no_dump_ptr flag for AST dump options in 'read_verilog' | Udi Finkelstein | 2018-08-23 | 1 | -1/+9 | |
| |/ | | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same. | |||||
| * | Merge pull request #591 from hzeller/virtual-override | Clifford Wolf | 2018-08-15 | 1 | -6/+6 | |
| |\ | | | | | Consistent use of 'override' for virtual methods in derived classes. | |||||
| | * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -6/+6 | |
| | | | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | |||||
| * | | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 2 | -2/+7 | |
| |\ \ | | | | | | | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test) | |||||
| | * | | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -0/+1 | |
| | | | | | | | | | | | | | No longer false warnings for memories and assertions | |||||
| | * | | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 2 | -2/+6 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) | |||||
| * | | | Merge pull request #562 from udif/pr_fix_illegal_port_decl | Clifford Wolf | 2018-08-15 | 1 | -3/+6 | |
| |\ \ \ | |_|/ |/| | | Detect illegal port declaration, e.g input/output/inout keyword must … | |||||
| | * | | Detect illegal port declaration, e.g input/output/inout keyword must be the ↵ | Udi Finkelstein | 2018-06-06 | 1 | -3/+6 | |
| | | | | | | | | | | | | | first. | |||||
| * | | | Convert more log_error() to log_file_error() where possible. | Henner Zeller | 2018-07-20 | 1 | -5/+3 | |
| | | | | | | | | | | | | | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion. | |||||
| * | | | Use log_file_warning(), log_file_error() functions. | Henner Zeller | 2018-07-20 | 1 | -5/+3 | |
| |/ / | | | | | | | Wherever we can report a source-level location. | |||||
| * | | Support SystemVerilog `` extension for macros | Jim Paris | 2018-05-17 | 1 | -1/+5 | |
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| * | | Skip spaces around macro arguments | Jim Paris | 2018-05-17 | 1 | -0/+1 | |
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| * | | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 1 | -6/+17 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Support more character literals | Dan Gisselquist | 2018-05-03 | 1 | -1/+9 | |
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| * | | Add statement labels for immediate assertions | Clifford Wolf | 2018-04-13 | 1 | -18/+21 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Allow "property" in immediate assertions | Clifford Wolf | 2018-04-12 | 1 | -17/+20 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add read_verilog anyseq/anyconst/allseq/allconst attribute support | Clifford Wolf | 2018-04-06 | 1 | -1/+33 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | First draft of Verilog parser support for specify blocks and parameters. | Udi Finkelstein | 2018-03-27 | 2 | -2/+170 | |
| |/ | | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST | |||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -1/+3 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add support for "yosys -E" | Clifford Wolf | 2018-01-07 | 1 | -2/+4 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Bugfix in verilog_defaults argument parser | Clifford Wolf | 2017-12-24 | 1 | -1/+1 | |
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| * | Add Verilog "automatic" keyword (ignored in synthesis) | Clifford Wolf | 2017-11-23 | 2 | -13/+18 | |
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| * | Accept real-valued delay values | Clifford Wolf | 2017-11-18 | 1 | -0/+1 | |
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| * | Accommodate Windows-style paths during include-file processing. | William D. Jones | 2017-11-14 | 1 | -4/+20 | |
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| * | Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the ↵ | Udi Finkelstein | 2017-09-30 | 1 | -3/+5 | |
| | | | | | | | textbook solution (Oreilly 'Flex & Bison' page 189) | |||||
| * | Minor coding style fix | Clifford Wolf | 2017-09-26 | 1 | -1/+1 | |
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| * | Merge branch 'master' of https://github.com/combinatorylogic/yosys into ↵ | Clifford Wolf | 2017-09-26 | 1 | -41/+69 | |
| |\ | | | | | | | combinatorylogic-master | |||||
| | * | Adding support for string macros and macros with arguments after include | combinatorylogic | 2017-09-21 | 1 | -41/+69 | |
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| * | | Fix ignoring of simulation timings so that invalid module parameters cause ↵ | Clifford Wolf | 2017-09-26 | 2 | -4/+2 | |
| |/ | | | | syntax errors | |||||
| * | Add a paragraph about pre-defined macros to read_verilog help message | Clifford Wolf | 2017-07-21 | 1 | -0/+4 | |
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| * | Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵ | Clifford Wolf | 2017-06-07 | 1 | -0/+1 | |
| | | | | | const reg" | |||||
| * | Fix handling of Verilog ~& and ~| operators | Clifford Wolf | 2017-06-01 | 1 | -0/+8 | |
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| * | Add support for localparam in module header | Clifford Wolf | 2017-04-30 | 1 | -1/+7 | |
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| * | Add support for `resetall compiler directive | Clifford Wolf | 2017-04-26 | 1 | -0/+7 | |
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| * | Fix verilog pre-processor for multi-level relative includes | Clifford Wolf | 2017-03-14 | 1 | -4/+26 | |
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| * | Allow $anyconst, etc. in non-formal SV mode | Clifford Wolf | 2017-03-01 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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