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* | Allow "property" in immediate assertionsClifford Wolf2018-04-121-17/+20
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add read_verilog anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-1/+33
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-272-2/+170
|/ | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for "yosys -E"Clifford Wolf2018-01-071-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in verilog_defaults argument parserClifford Wolf2017-12-241-1/+1
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* Add Verilog "automatic" keyword (ignored in synthesis)Clifford Wolf2017-11-232-13/+18
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* Accept real-valued delay valuesClifford Wolf2017-11-181-0/+1
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* Accommodate Windows-style paths during include-file processing.William D. Jones2017-11-141-4/+20
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* Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the ↵Udi Finkelstein2017-09-301-3/+5
| | | | | | textbook solution (Oreilly 'Flex & Bison' page 189)
* Minor coding style fixClifford Wolf2017-09-261-1/+1
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* Merge branch 'master' of https://github.com/combinatorylogic/yosys into ↵Clifford Wolf2017-09-261-41/+69
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| * Adding support for string macros and macros with arguments after includecombinatorylogic2017-09-211-41/+69
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* | Fix ignoring of simulation timings so that invalid module parameters cause ↵Clifford Wolf2017-09-262-4/+2
|/ | | | syntax errors
* Add a paragraph about pre-defined macros to read_verilog help messageClifford Wolf2017-07-211-0/+4
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* Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵Clifford Wolf2017-06-071-0/+1
| | | | const reg"
* Fix handling of Verilog ~& and ~| operatorsClifford Wolf2017-06-011-0/+8
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* Add support for localparam in module headerClifford Wolf2017-04-301-1/+7
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* Add support for `resetall compiler directiveClifford Wolf2017-04-261-0/+7
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* Fix verilog pre-processor for multi-level relative includesClifford Wolf2017-03-141-4/+26
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* Allow $anyconst, etc. in non-formal SV modeClifford Wolf2017-03-011-1/+1
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* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-252-1/+28
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* Add support for SystemVerilog unique, unique0, and priority caseClifford Wolf2017-02-232-4/+25
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* Added SystemVerilog support for ++ and --Clifford Wolf2017-02-232-1/+12
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* Add checker support to verilog front-endClifford Wolf2017-02-092-11/+24
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* Add SV "rand" and "const rand" supportClifford Wolf2017-02-082-8/+28
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* Further improve cover() supportClifford Wolf2017-02-041-0/+6
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* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-042-1/+8
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* Add "enum" and "typedef" lexer supportClifford Wolf2017-01-172-1/+4
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* Added "verilog_defines" commandClifford Wolf2016-12-151-0/+60
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* Added support for macros as include file namesClifford Wolf2016-11-281-0/+2
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* Bugfix in "read_verilog -D NAME=VAL" handlingClifford Wolf2016-11-281-3/+3
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* Added support for hierarchical defparamsClifford Wolf2016-11-151-3/+2
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* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-153-3/+17
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* Added $anyseq cell typeClifford Wolf2016-10-141-1/+1
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* Removed $aconst cell typeClifford Wolf2016-08-301-1/+1
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* Removed $predict againClifford Wolf2016-08-282-8/+1
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* Added read_verilog -norestrict -assume-assertsClifford Wolf2016-08-264-5/+40
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* Improved verilog parser errorsClifford Wolf2016-08-251-0/+3
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* Added SV "restrict" keywordClifford Wolf2016-08-241-1/+2
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* Fixed bug in parsing real constantsClifford Wolf2016-08-061-4/+4
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* Added $anyconst and $aconstClifford Wolf2016-07-271-1/+1
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* Added "read_verilog -dump_rtlil"Clifford Wolf2016-07-271-1/+9
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* Fixed a verilog parser memory leakClifford Wolf2016-07-251-0/+1
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* Fixed parsing of empty positional cell portsClifford Wolf2016-07-251-2/+31
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* No tristate warning message for "read_verilog -lib"Clifford Wolf2016-07-233-8/+11
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* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-0/+2
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* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-212-6/+10
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* Added basic support for $expect cellsClifford Wolf2016-07-132-1/+9
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* Allow defining input ports as "input logic" in SystemVerilogRuben Undheim2016-06-201-2/+2
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