aboutsummaryrefslogtreecommitdiffstats
path: root/frontends
Commit message (Collapse)AuthorAgeFilesLines
* Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-0/+5
| | | | This reverts commit 2dffa4685b830313204f5d04314a14ed6ecac8ec.
* Add "-W' wire delay arg to abc9, use from synth_xilinxEddie Hung2019-06-111-5/+0
|
* Fine tune aigerparseEddie Hung2019-06-071-62/+27
|
* Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-077-832/+924
|\
| * Fix spacing from spaces to tabsEddie Hung2019-06-071-362/+362
| |
| * Fix spacing (entire file is wrong anyway, will fix later)Eddie Hung2019-06-071-3/+3
| |
| * Remove unnecessary std::getline() for ASCIIEddie Hung2019-06-071-3/+0
| |
| * Fix read_aiger -- create zero driver, fix init width, parse 'b'Eddie Hung2019-06-072-13/+52
| |
| * Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-073-46/+34
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-076-5/+64
| |\ | | | | | | | | | clifford/pr983
| | * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-036-5/+64
| | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
| * | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-071-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-071-1/+10
| |\ \ | | | | | | | | | | | | into tux3-implicit_named_connection
| | * | SystemVerilog support for implicit named port connectionstux32019-06-061-9/+17
| | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
* | | | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7muxEddie Hung2019-06-061-10/+14
|\| | |
| * | | Merge pull request #1060 from antmicro/parsing_attr_on_port_connClifford Wolf2019-06-061-10/+14
| |\ \ \ | | |/ / | |/| | Added support for parsing attributes on port connections.
| | * | Fixed memory leak.Maciej Kurc2019-06-051-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| | * | Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
| | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-031-0/+11
|\| | |
| * | | Only support Symbiotic EDA flavored VerificClifford Wolf2019-06-021-0/+8
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ↵Clifford Wolf2019-05-301-0/+3
| | | | | | | | | | | | | | | | | | fixes #1055 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Assert that box_unique_id is indeed uniqueEddie Hung2019-06-031-2/+3
| | |
* | | Skip internal modules when generating box_unique_idEddie Hung2019-06-031-0/+1
| | |
* | | parse_xaiger to cope with flopsEddie Hung2019-05-312-83/+123
| | |
* | | Merge branch 'xaig' into xc7muxEddie Hung2019-05-311-0/+18
|\ \ \
| * | | Move clean from aigerparse to abc9Eddie Hung2019-04-231-2/+0
| | | |
| * | | Tidy upEddie Hung2019-04-221-1/+1
| | | |
| * | | Revert "Temporarily remove 'r' extension"Eddie Hung2019-04-221-0/+18
| | | | | | | | | | | | | | | | This reverts commit eaf3c247729365cec776e147f380ce59f7dccd4d.
* | | | read_xaiger() to name box signalsEddie Hung2019-05-301-4/+8
| | | |
* | | | Remove whitespaceEddie Hung2019-05-301-1/+0
| | | |
* | | | Carry in/out to be the last input/output for chains to be preservedEddie Hung2019-05-301-0/+38
| | | |
* | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-286-15/+61
|\ \ \ \ | | |/ / | |/| |
| * | | Merge branch 'master' into wandworStefan Biereigel2019-05-275-14/+47
| |\ \ \
| | * \ \ Merge pull request #1044 from mmicko/invalid_width_rangeClifford Wolf2019-05-271-1/+2
| | |\ \ \ | | | | | | | | | | | | Give error instead of asserting for invalid range, fixes #947
| | | * | | Give error instead of asserting for invalid range, fixes #947Miodrag Milanovic2019-05-271-1/+2
| | | | | |
| | * | | | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-275-13/+45
| | |/ / / | | | | | | | | | | | | | | | Includes work from @sumit0190 and @AaronKel
| * | | | remove leftovers from ast data structuresStefan Biereigel2019-05-272-4/+0
| | | | |
| * | | | move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-97/+14
| | | | |
| * | | | fix assignment of non-wiresStefan Biereigel2019-05-231-16/+19
| | | | |
| * | | | fix indentation across filesStefan Biereigel2019-05-234-63/+83
| | | | |
| * | | | implementation for assignments workingStefan Biereigel2019-05-233-14/+83
| | | | |
| * | | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-233-2/+10
| |/ / /
* | | | read_aiger to only clean own designEddie Hung2019-05-281-0/+6
| | | |
* | | | Parse "a" extension and boxes from map fileEddie Hung2019-05-271-41/+60
| | | |
* | | | Remove unused functionEddie Hung2019-05-271-23/+0
| | | |
* | | | parse_xaiger to not parse symbol tableEddie Hung2019-05-271-64/+0
| | | |
* | | | Instantiate cell type (from sym file) otherwise 'clean' warningsEddie Hung2019-05-271-3/+6
| | | |
* | | | Add 'cinput' and 'coutput' to symbols file for boxesEddie Hung2019-05-271-0/+35
| | | |
* | | | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7muxEddie Hung2019-05-231-5/+9
|\| | |
| * | | Rename labelEddie Hung2019-05-211-6/+5
| | | |
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-24 19:17:41 +0000