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| * | | | Improve $specrule interfaceClifford Wolf2019-04-232-9/+19
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Improve $specrule interfaceClifford Wolf2019-04-231-20/+18
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-234-4/+86
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Allow $specify[23] cells in blackbox modulesClifford Wolf2019-04-231-0/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Checking and fixing specify cells in genRTLILClifford Wolf2019-04-231-1/+15
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Add specify parserClifford Wolf2019-04-234-33/+243
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-061-2/+0
|\ \ \ \ \ | | | | | | | | | | | | Re-enable "final loop assignment" feature and fix opt_clean warnings
| * \ \ \ \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-065-4/+15
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| * | | | | | Re-enable "final loop assignment" featureClifford Wolf2019-05-011-2/+0
| | |_|_|_|/ | |/| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-062-26/+71
|\ \ \ \ \ \ | |_|/ / / / |/| | | | | Improve verific -chparam and add hierarchy -chparam
| * | | | | For hier_tree::Elaborate() also include SV root modules (bind)Eddie Hung2019-05-031-23/+36
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| * | | | | Fix verific_parameters construction, use attribute to mark top netlistsEddie Hung2019-05-032-8/+12
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| * | | | | WIP -chparam support for hierarchy when verificEddie Hung2019-05-032-12/+17
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| * | | | | verific_import() changes to avoid ElaborateAll()Eddie Hung2019-05-031-15/+38
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* | | | | Fix the other bison warning in ilang_parser.yClifford Wolf2019-05-061-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | verilog_parser: Fix Bison warningBen Widawsky2019-05-051-1/+1
| |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of Bison 2.6, name-prefix is deprecated. This fixes frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated] %name-prefix "frontend_verilog_yy" For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html Compile tested only. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* | | | Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-042-1/+5
|\ \ \ \ | | | | | | | | | | Add approximate support for SV "var" keyword
| * | | | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-042-1/+5
| |/ / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / / / Add support for SVA "final" keywordClifford Wolf2019-05-042-1/+5
|/ / / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix width detection of memory access with bit slice, fixes #974Clifford Wolf2019-05-011-0/+2
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Disabled "final loop assignment" featureClifford Wolf2019-04-301-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #972 from YosysHQ/clifford/fix968Clifford Wolf2019-04-301-0/+7
|\ \ | | | | | | Add final loop variable assignment when unrolling for-loops
| * | Add final loop variable assignment when unrolling for-loops, fixes #968Clifford Wolf2019-04-301-0/+7
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / Include filename in "Executing Verilog-2005 frontend" message, fixes #959Clifford Wolf2019-04-301-2/+2
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #952 from YosysHQ/clifford/fix370Clifford Wolf2019-04-221-3/+18
|\ | | | | Determine correct signedness and expression width in for-loop unrolling
| * Determine correct signedness and expression width in for loop unrolling, ↵Clifford Wolf2019-04-221-3/+18
| | | | | | | | | | | | fixes #370 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add log_debug() frameworkClifford Wolf2019-04-221-2/+0
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #909 from zachjs/masterClifford Wolf2019-04-221-1/+20
|\ | | | | support repeat loops with constant repeat counts outside of constant functions
| * support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-091-1/+20
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* | Add "noblackbox" attributeClifford Wolf2019-04-211-17/+27
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | New behavior for front-end handling of whiteboxesClifford Wolf2019-04-205-34/+100
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-185-11/+42
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "read_ilang -lib"Clifford Wolf2019-04-053-3/+14
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906Clifford Wolf2019-03-291-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "read -verific" and "read -noverific"Clifford Wolf2019-03-271-6/+28
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix "verific -extnets" for more complex situationsClifford Wolf2019-03-261-15/+71
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix mem2reg handling of memories with upto data ports, fixes #888Clifford Wolf2019-03-211-1/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve "read_verilog -dump_vlog[12]" handling of upto rangesClifford Wolf2019-03-211-3/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve read_verilog debug output capabilitiesClifford Wolf2019-03-213-15/+42
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-03-198-110/+348
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| * fix local name resolution in prefix constructsZachary Snow2019-03-181-1/+5
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| * Improve handling of "full_case" attributesClifford Wolf2019-03-141-0/+9
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve handling of memories used in mem index expressions on LHS of an ↵Clifford Wolf2019-03-121-5/+16
| | | | | | | | | | | | assignment Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Remove outdated "blocking assignment to memory" warningClifford Wolf2019-03-121-10/+0
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867Clifford Wolf2019-03-121-6/+8
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-102-92/+66
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #858 from YosysHQ/clifford/svalabelsClifford Wolf2019-03-095-56/+201
| |\ | | | | | | Add support for using SVA labels in yosys-smtbmc console output
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