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* Merge pull request #1607 from whitequark/simplify-simplify-meminitClaire Wolf2020-03-271-63/+82
|\ | | | | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
| * ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.whitequark2020-02-071-65/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
* | Simplify was not being called for packages. Broke typedef enums.Peter Crozier2020-03-221-5/+8
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* | Build pkg_user_types before parsing in case of changes in the design.Peter Crozier2020-03-221-6/+3
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* | Clear pkg_user_types if no packages following a 'design -reset-vlog'.Peter2020-03-222-0/+5
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* | Parser changes to support typedef.Peter2020-03-224-10/+88
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* | Merge pull request #1788 from YosysHQ/eddie/fix_ndebugEddie Hung2020-03-192-2/+2
|\ \ | | | | | | Fix NDEBUG warnings
| * | Fix NDEBUG warningsEddie Hung2020-03-192-2/+2
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* | | Merge pull request #1787 from YosysHQ/mmicko/lexer_depsMiodrag Milanović2020-03-191-1/+1
|\ \ \ | |/ / |/| | Add dependency to verilog_lexer.cc
| * | Add one mode dependencyMiodrag Milanovic2020-03-191-1/+1
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* | | Merge pull request #1775 from huaixv/asserts_locationsN. Engelhardt2020-03-192-7/+31
|\ \ \ | |/ / |/| | Add precise locations for asserts
| * | Add precise locations for assertshuaixv2020-03-192-7/+31
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* | | Add AST node source location information in a couple more parser rules.Alberto Gonzalez2020-03-171-0/+2
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* | Merge pull request #1759 from zeldin/constant_with_comment_reduxMiodrag Milanović2020-03-142-19/+43
|\ \ | | | | | | refixed parsing of constant with comment between size and value
| * | refixed parsing of constant with comment between size and valueMarcus Comstedt2020-03-112-19/+43
| | | | | | | | | | | | | | | | | | The three parts of a based constant (size, base, digits) are now three separate tokens, allowing the linear whitespace (including comments) between them to be treated as normal inter-token whitespace.
* | | Merge pull request #1754 from boqwxp/precise_locationsMiodrag Milanović2020-03-141-2/+53
|\ \ \ | | | | | | | | Set AST node source location in more parser rules.
| * | | verilog: also set location for simple_behavioral_stmtEddie Hung2020-03-101-0/+4
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| * | | Set AST source locations in more parser rules.Alberto Gonzalez2020-03-101-2/+49
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* / / Fix compilation for emccjiegec2020-03-111-1/+2
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* | Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-081-4/+6
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Fix bison warning for "pure-parser" optionClaire Wolf2020-03-031-1/+1
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-038-299/+384
|\ \ | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * | Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-238-299/+384
| | | | | | | | | | | | and RTLIL nodes.
* | | Merge pull request #1681 from YosysHQ/eddie/fix1663Claire Wolf2020-03-031-15/+13
|\ \ \ | | | | | | | | verilog: instead of modifying localparam size, extend init constant expr
| * | | verilog: instead of modifying localparam size, extend init constant exprEddie Hung2020-02-051-15/+13
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* | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-022-12/+20
|\ \ \ | | | | | | | | abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
| * | | ast: quiet down when deriving blackbox modulesEddie Hung2020-02-272-12/+20
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* | | ast: fixes #1710; do not generate RTLIL for unreachable ternaryEddie Hung2020-02-271-9/+22
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* | | Comment out log()Eddie Hung2020-02-271-1/+1
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* | Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-213-36/+92
|\ \ | | | | | | Improve specify parser
| * | verilog: add support for more delays than just rise/fallEddie Hung2020-02-191-1/+40
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| * | verilog: ignore ranges too without -specifyEddie Hung2020-02-131-1/+2
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| * | verilog: improve specify support when not in -specify modeEddie Hung2020-02-131-13/+7
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| * | verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-132-5/+6
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| * | specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-12/+29
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| * | verilog: fix $specify3 checkEddie Hung2020-02-131-7/+11
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* | | Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-205-18/+325
|\ \ \ | |/ / |/| | Enum support
| * | remove unnecessary blank lineJeff Wang2020-02-171-2/+1
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| * | add attributes for enumerated values in ilangJeff Wang2020-02-173-2/+76
| | | | | | | | | | | | | | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
| * | separate out enum_item/param implementation when they should be differentJeff Wang2020-02-171-7/+16
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| * | fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6Jeff Wang2020-01-171-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | The if(str == node->str) is in fact necessary (otherwise causes generate for in Multiplier_2D in tests/simple/multiplier.v to fail with error message "Right hand side of 3rd expression of generate for-loop is not constant!"). Note: in PeterCrozier's implementation, the break only breaks out of the switch-case, not the outer for loop.
| * | fix enum in generate blocksJeff Wang2020-01-161-0/+20
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| * | allow enums to be declared at toplevel scopeJeff Wang2020-01-161-0/+7
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| * | lexer doesn't seem to return TOK_REG for logic anymoreJeff Wang2020-01-161-3/+4
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| * | allow enum typedefsJeff Wang2020-01-161-1/+6
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| * | partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-165-17/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* | | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-131-2/+2
|\ \ \ | | | | | | | | Fix crash on wire declaration with delay
| * | | correct wire declaration grammar for #1614Stefan Biereigel2020-02-031-2/+2
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* | | | Modified $readmem[hb] to use '\' or '/' according the OSRodrigo Alejandro Melo2020-02-061-1/+6
| | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
* | | | Merge branch 'master' of https://github.com/YosysHQ/yosysRodrigo Alejandro Melo2020-02-034-94/+118
|\ \ \ \ | | |_|/ | |/| | | | | | | | | | | | | | Solved a conflict into the CHANGELOG Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
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