iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	$size() now works correctly for all cases!	Udi Finkelstein	2017-09-26	1	-17/+17
\| \| \| \|	It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
*	$size() seems to work now with or without the optional parameter.	Udi Finkelstein	2017-09-26	1	-10/+40
\| \| \| \|	Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
*	enable $bits() and $size() functions only when the SystemVerilog flag is ↵	Udi Finkelstein	2017-09-26	1	-1/+1
\| \| \| \|	enabled for read_verilog
*	Added $bits() for memories as well.	Udi Finkelstein	2017-09-26	1	-2/+26
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*	$size() now works with memories as well!	Udi Finkelstein	2017-09-26	1	-1/+3
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*	Add $size() function. At the moment it works only on expressions, not on ↵	Udi Finkelstein	2017-09-26	1	-0/+14
\| \| \| \|	memories.
*	Increase maximum LUT size in blifparse to 12 bits	Clifford Wolf	2017-09-27	1	-1/+1
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*	Parse reals as string in JSON front-end	Clifford Wolf	2017-09-26	1	-0/+28
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*	Minor coding style fix	Clifford Wolf	2017-09-26	1	-1/+1
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*	Merge branch 'master' of https://github.com/combinatorylogic/yosys into ↵	Clifford Wolf	2017-09-26	1	-41/+69
\|\ \| \| \| \| \| \|	combinatorylogic-master
\| *	Adding support for string macros and macros with arguments after include	combinatorylogic	2017-09-21	1	-41/+69
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* \|	Fix ignoring of simulation timings so that invalid module parameters cause ↵	Clifford Wolf	2017-09-26	2	-4/+2
\|/ \| \| \|	syntax errors
*	json: Parse inout correctly rather than as an output	Robert Ou	2017-08-14	1	-0/+1
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*	Add merging of "past FFs" to verific importer	Clifford Wolf	2017-07-29	1	-2/+76
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*	Add minimal support for PSL in VHDL via Verific	Clifford Wolf	2017-07-28	1	-19/+155
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*	Improve Verific HDL language options	Clifford Wolf	2017-07-28	1	-4/+4
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*	Fix handling of non-user-declared Verific netbus	Clifford Wolf	2017-07-28	1	-2/+3
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*	Improve Verific SVA importer	Clifford Wolf	2017-07-27	1	-0/+34
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*	Add log_warning_noprefix() API, Use for Verific warnings and errors	Clifford Wolf	2017-07-27	1	-1/+1
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*	Add "verific -import -n" and "verific -import -nosva"	Clifford Wolf	2017-07-27	1	-14/+36
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*	Improve Verific SVA import: negedge and $past	Clifford Wolf	2017-07-27	1	-6/+49
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*	Improve Verific SVA importer	Clifford Wolf	2017-07-27	1	-37/+58
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*	Improve Verific bindings (mostly related to SVA)	Clifford Wolf	2017-07-26	1	-110/+320
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*	Improve "help verific" message	Clifford Wolf	2017-07-25	1	-5/+5
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*	Add "verific -extnets"	Clifford Wolf	2017-07-25	1	-23/+130
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*	Improve "verific -all" handling	Clifford Wolf	2017-07-25	1	-26/+45
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*	Add "verific -import -d <dump_file"	Clifford Wolf	2017-07-24	1	-6/+35
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*	Add "verific -import -flatten" and "verific -import -v"	Clifford Wolf	2017-07-24	1	-107/+164
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*	Add "verific -import -k"	Clifford Wolf	2017-07-22	1	-42/+51
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*	Improve docs for verific bindings, add simply sby example	Clifford Wolf	2017-07-22	5	-48/+89
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*	Fix "read_blif -wideports" handling of cells with wide ports	Clifford Wolf	2017-07-21	1	-3/+33
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*	Add a paragraph about pre-defined macros to read_verilog help message	Clifford Wolf	2017-07-21	1	-0/+4
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*	Add attributes and parameter support to JSON front-end	Clifford Wolf	2017-07-10	1	-7/+50
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*	Add JSON front-end	Clifford Wolf	2017-07-08	2	-0/+472
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*	Add Verific Release information to log	Clifford Wolf	2017-07-04	1	-0/+12
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*	Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵	Clifford Wolf	2017-06-07	2	-0/+8
\| \| \| \|	const reg"
*	Fix handling of Verilog ~& and ~\| operators	Clifford Wolf	2017-06-01	1	-0/+8
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*	Add support for localparam in module header	Clifford Wolf	2017-04-30	1	-1/+7
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*	Add support for `resetall compiler directive	Clifford Wolf	2017-04-26	1	-0/+7
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*	Fix verilog pre-processor for multi-level relative includes	Clifford Wolf	2017-03-14	1	-4/+26
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*	Allow $anyconst, etc. in non-formal SV mode	Clifford Wolf	2017-03-01	1	-1/+1
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*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	6	-4/+40
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*	Add support for SystemVerilog unique, unique0, and priority case	Clifford Wolf	2017-02-23	2	-4/+25
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*	Preserve string parameters	Clifford Wolf	2017-02-23	1	-2/+8
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*	Added SystemVerilog support for ++ and --	Clifford Wolf	2017-02-23	2	-1/+12
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*	Fix incorrect "incompatible re-declaration of wire" error in tasks/functions	Clifford Wolf	2017-02-14	1	-2/+9
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*	Add support for verific mem initialization	Clifford Wolf	2017-02-11	1	-0/+38
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*	Fix another stupid bug in the same line	Clifford Wolf	2017-02-11	1	-1/+1
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*	Add verific support for initialized variables	Clifford Wolf	2017-02-11	1	-3/+47
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*	Improve handling of Verific warnings and error messages	Clifford Wolf	2017-02-11	1	-4/+10
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