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| * | verific: rewrite initial assume/asserts prior to elaborationEddie Hung2020-05-151-17/+36
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* | | Merge pull request #2203 from antmicro/fix-grammarclairexen2020-07-011-4/+10
|\ \ \ | | | | | | | | Signed and macro grammar update
| * | | Parse macro call attached semicolon as empty expressionLukasz Dalek2020-06-261-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * | | Fix integer signing grammarLukasz Dalek2020-06-261-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes signed/unsigned grammar in parameters as defined in SV LRM A2.2.1. Example of correct parameters: parameter integer signed i = 0; parameter integer unsigned i = 0; Example of incorrect parameters: parameter signed integer i = 0; parameter unsigned integer i = 0; Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | | | Merge pull request #2179 from splhack/static-castclairexen2020-07-016-0/+55
|\ \ \ \ | | | | | | | | | | Support SystemVerilog Static Cast
| * | | | static cast: simplifyKazuki Sakamoto2020-06-191-0/+7
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| * | | | static cast: support changing size and signednessKazuki Sakamoto2020-06-196-0/+48
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* | | | Merge pull request #2136 from zachjs/masterclairexen2020-06-301-1/+5
|\ \ \ \ | | | | | | | | | | Allow constant function calls in for loops and generate if and case
| * | | | Allow constant function calls in for loops and generate if and caseZachary Snow2020-06-291-1/+5
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* | | | | Update verific API version checkMiodrag Milanovic2020-06-301-1/+1
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* | | | Fix crash in verific frontendMiodrag Milanovic2020-06-261-1/+2
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* | | | Merge pull request #2188 from antmicro/missing-operatorswhitequark2020-06-262-2/+49
|\ \ \ \ | | | | | | | | | | Add logic-assignments operators
| * | | | Support missing sub-assign and and-assign operatorsKamil Rakoczy2020-06-252-2/+21
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | Support missing xor-assign operatorLukasz Dalek2020-06-242-1/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * | | | Add plus-assignment operatorKamil Rakoczy2020-06-242-1/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | Add or-assignment operatorKamil Rakoczy2020-06-242-1/+11
| |/ / / | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | | | Merge pull request #2189 from antmicro/optional-labelswhitequark2020-06-261-2/+2
|\ \ \ \ | | | | | | | | | | Add support for optional labels
| * | | | Support optional labels at the end of package definitionLukasz Dalek2020-06-241-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * | | | Support optional labels at the end of module definitionLukasz Dalek2020-06-241-1/+1
| |/ / / | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | | | Merge pull request #2168 from whitequark/assert-unused-exprsclairexen2020-06-253-12/+12
|\ \ \ \ | | | | | | | | | | Use (and ignore) the expression provided to log_assert in NDEBUG builds
| * | | | Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().whitequark2020-06-193-12/+12
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* | | | optimization, all items should have same attributesMiodrag Milanovic2020-06-251-0/+1
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* | | | verific - import attributes for net buses as wellMiodrag Milanovic2020-06-241-1/+4
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* | | Use C++11 final/override keywords.whitequark2020-06-189-34/+34
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* | | MSVC does not understand __builtin_unreachableAnonymous Maarten2020-06-171-1/+1
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* | | MSVC cannot omit operand in conditionalAnonymous Maarten2020-06-171-1/+1
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* | | Merge pull request #2131 from YosysHQ/claire/preserveffsclairexen2020-06-101-0/+3
|\ \ \ | | | | | | | | Do not optimize away FFs in "prep" and Verific front-end
| * | | Do not optimize away FFs in "prep" and Verific fron-endClaire Wolf2020-06-091-0/+3
| | |/ | |/| | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | verific - detect missing memory to prevent crash.Miodrag Milanovic2020-06-101-2/+7
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* | | Merge pull request #2112 from YosysHQ/claire/fix2040clairexen2020-06-092-0/+58
|\ \ \ | |/ / |/| | Add latch detection for use_case_method in part-select write
| * | Add latch detection for use_case_method in part-select write, fixes #2040Claire Wolf2020-06-042-0/+58
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Support packed arrays in struct/union.Peter Crozier2020-06-072-17/+136
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* | Merge pull request #2041 from PeterCrozier/structclairexen2020-06-046-204/+526
|\ \ | | | | | | Implementation of SV structs.
| * \ Merge branch 'master' into structPeter Crozier2020-06-038-53/+95
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| * | | Allow structs within structs.Peter Crozier2020-05-121-7/+18
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| * | | Generalise structs and add support for packed unions.Peter Crozier2020-05-126-58/+147
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| * | | Implement SV structs.Peter Crozier2020-05-086-205/+427
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* | | | Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-2/+5
|\ \ \ \ | | | | | | | | | | abc9: -dff improvements
| * | | | aiger: cleanupEddie Hung2020-05-251-2/+5
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* | | | | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-043-1/+10
|\ \ \ \ \ | |_|_|/ / |/| | | | Preserve 'signed'-ness of a verilog wire through RTLIL
| * | | | frontends/json/jsonparse.cc: Like the upto field read_json can also read the ↵Vamsi K Vytla2020-04-271-1/+6
| | | | | | | | | | | | | | | | | | | | signedness of a wire
| * | | | Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-272-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser
* | | | | Support asymmetric memories for verific frontendMiodrag Milanovic2020-06-011-6/+1
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* | | | | Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logicclairexen2020-05-291-2/+2
|\ \ \ \ \ | | | | | | | | | | | | ast/simplify: don't bitblast async ROMs declared as `logic`
| * | | | | ast/simplify: don't bitblast async ROMs declared as `logic`.whitequark2020-05-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fixes #2020.
* | | | | | Merge pull request #2097 from whitequark/ilang_lexer-fix-erangewhitequark2020-05-291-1/+3
|\ \ \ \ \ \ | | | | | | | | | | | | | | ilang_lexer: fix check for out of range literal
| * | | | | | ilang_lexer: fix check for out of range literal.whitequark2020-05-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ca70a104 did not use a correct check.
* | | | | | | Merge pull request #2033 from boqwxp/cleanup-verilog-lexerwhitequark2020-05-291-6/+5
|\ \ \ \ \ \ \ | |/ / / / / / |/| | | | | | verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
| * | | | | | verilog: Move lexer location variables from global namespace to ↵Alberto Gonzalez2020-05-061-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | `VERILOG_FRONTEND` namespace.
* | | | | | | Silence spurious warning in Verilog lexer when compiling with GCCRupert Swarbrick2020-05-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The chosen value shouldn't have any effect. I considered something clearly wrong like -1, but there's no checking inside the generated lexer, and I suspect this will cause even weirder bugs if triggered than just setting it to INITIAL.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 17:16:21 +0000