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* Fix for using POSIX basenameEddie Hung2019-02-191-2/+4
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* Missing OSX headers?Eddie Hung2019-02-171-0/+5
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* read_aiger to ignore line after ands for ascii, not binaryEddie Hung2019-02-171-2/+1
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* Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-02-171-5/+4
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| * Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aigerEddie Hung2019-02-121-3/+1
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| * | Do not break for constraintsEddie Hung2019-02-111-1/+0
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| * | No increment line_count for binary ANDsEddie Hung2019-02-111-1/+1
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| * | Do not ignore newline after AND in binary AIGEddie Hung2019-02-111-1/+0
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* | | Use module->add{Not,And}Gate() functionsEddie Hung2019-02-121-8/+2
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* | addDff -> addDffGate as per @daveshah1Eddie Hung2019-02-081-1/+1
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* | Fix tabulationEddie Hung2019-02-081-28/+28
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* | -module_name arg to go before -clk_nameEddie Hung2019-02-081-7/+7
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* | Add missing "[options]" to read_blif helpEddie Hung2019-02-081-1/+1
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* | Allow module name to be determined by argument tooEddie Hung2019-02-082-14/+44
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* | Refactor into AigerReader classEddie Hung2019-02-082-79/+92
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* | Parse binary AIG filesEddie Hung2019-02-081-49/+164
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* | Refactor to parse_aiger_header()Eddie Hung2019-02-081-26/+32
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* | Add commentEddie Hung2019-02-081-0/+1
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* | Handle reset logic in latchesEddie Hung2019-02-081-2/+17
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* | Change literal vars from int to unsignedEddie Hung2019-02-081-1/+1
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* | Create clk outside of latch loopEddie Hung2019-02-081-7/+9
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* | Handle latch symbols tooEddie Hung2019-02-081-3/+1
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* | Remove return after log_errorEddie Hung2019-02-081-27/+9
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* | Add support for symbol tablesEddie Hung2019-02-081-1/+49
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* | Stub for binary AIGEREddie Hung2019-02-081-3/+8
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* | RefactorEddie Hung2019-02-061-1/+8
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* | WIPEddie Hung2019-02-063-0/+247
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* Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove -m32 Verific eval lib build instructionsClifford Wolf2019-01-041-29/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve VerificImporter support for writes to asymmetric memoriesClifford Wolf2019-01-021-22/+35
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix VerificImporter asymmetric memories error messageClifford Wolf2019-01-021-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-025-11/+11
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Add "read_ilang -[no]overwrite"Clifford Wolf2018-12-233-4/+54
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix segfault in AST simplifyClifford Wolf2018-12-181-0/+5
| | | | | | (as proposed by Dan Gisselquist) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve src tagging (using names and attrs) of cells and wires in verific ↵Clifford Wolf2018-12-182-99/+160
| | | | | | front-end Signed-off-by: Clifford Wolf <clifford@clifford.at>
* read_ilang: allow slicing sigspecs.whitequark2018-12-161-10/+6
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* verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
| | | | | | Fixes #737 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Verific updatesClifford Wolf2018-12-061-53/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make return value of $clog2 signedSylvain Munaut2018-11-241-1/+1
| | | | | | | | As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Set Verific flag vhdl_support_variable_slice=1Clifford Wolf2018-11-091-0/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Allow square brackets in liberty identifiersClifford Wolf2018-11-051-1/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Various indenting fixes in AST front-end (mostly space vs tab issues)Clifford Wolf2018-11-043-99/+69
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make and dependent upon LSB onlyZipCPU2018-11-031-2/+8
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* Do not generate "reg assigned in a continuous assignment" warnings for "rand ↵Clifford Wolf2018-11-011-2/+15
| | | | | | reg" Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #679 from udif/pr_syntax_errorClifford Wolf2018-10-251-14/+14
|\ | | | | More meaningful SystemVerilog/Verilog parser error messages
| * Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵Udi Finkelstein2018-10-251-14/+14
| | | | | | | | | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
* | Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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