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| | | * | Give error instead of asserting for invalid range, fixes #947Miodrag Milanovic2019-05-271-1/+2
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| | * | | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-275-13/+45
| | |/ / | | | | | | | | | | | | Includes work from @sumit0190 and @AaronKel
| * | | remove leftovers from ast data structuresStefan Biereigel2019-05-272-4/+0
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| * | | move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-97/+14
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| * | | fix assignment of non-wiresStefan Biereigel2019-05-231-16/+19
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| * | | fix indentation across filesStefan Biereigel2019-05-234-63/+83
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| * | | implementation for assignments workingStefan Biereigel2019-05-233-14/+83
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| * | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-233-2/+10
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| * | Rename labelEddie Hung2019-05-211-6/+5
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| * | Try againEddie Hung2019-05-211-4/+10
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| * | Fix warningEddie Hung2019-05-211-3/+2
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| * | Read bigger Verilog files.Kaj Tuomi2019-05-181-1/+1
| | | | | | | | | | | | Hit parser limit with 3M gate design. This commit fix it.
| * | Merge pull request #1013 from antmicro/parameter_attributesClifford Wolf2019-05-161-2/+2
| |\ \ | | | | | | | | Support for attributes on parameters and localparams for Verilog frontend
| | * | Added support for parsing attributes on parameters in Verilog frontent. ↵Maciej Kurc2019-05-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Content of those attributes is ignored. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-142-2/+18
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| * | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-068-35/+366
| |\ \ | | | | | | | | Add specify parser
| | * | Add "real" keyword to ilang formatClifford Wolf2019-05-062-1/+8
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-062-2/+10
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| | * | | Improve write_verilog specify supportClifford Wolf2019-05-041-0/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-033-2/+14
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| | * | | | Improve $specrule interfaceClifford Wolf2019-04-232-9/+19
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Improve $specrule interfaceClifford Wolf2019-04-231-20/+18
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-234-4/+86
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Allow $specify[23] cells in blackbox modulesClifford Wolf2019-04-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Checking and fixing specify cells in genRTLILClifford Wolf2019-04-231-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Add specify parserClifford Wolf2019-04-234-33/+243
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-061-2/+0
| |\ \ \ \ \ | | | | | | | | | | | | | | Re-enable "final loop assignment" feature and fix opt_clean warnings
| | * \ \ \ \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-065-4/+15
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| | * | | | | | Re-enable "final loop assignment" featureClifford Wolf2019-05-011-2/+0
| | | |_|_|_|/ | | |/| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-062-26/+71
| |\ \ \ \ \ \ | | |_|/ / / / | |/| | | | | Improve verific -chparam and add hierarchy -chparam
| | * | | | | For hier_tree::Elaborate() also include SV root modules (bind)Eddie Hung2019-05-031-23/+36
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| | * | | | | Fix verific_parameters construction, use attribute to mark top netlistsEddie Hung2019-05-032-8/+12
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| | * | | | | WIP -chparam support for hierarchy when verificEddie Hung2019-05-032-12/+17
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| | * | | | | verific_import() changes to avoid ElaborateAll()Eddie Hung2019-05-031-15/+38
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| * | | | | Fix the other bison warning in ilang_parser.yClifford Wolf2019-05-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | verilog_parser: Fix Bison warningBen Widawsky2019-05-051-1/+1
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of Bison 2.6, name-prefix is deprecated. This fixes frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated] %name-prefix "frontend_verilog_yy" For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html Compile tested only. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | | | Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-042-1/+5
| |\ \ \ \ | | | | | | | | | | | | Add approximate support for SV "var" keyword
| | * | | | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-042-1/+5
| | |/ / / | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * / / / Add support for SVA "final" keywordClifford Wolf2019-05-042-1/+5
| |/ / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Fix width detection of memory access with bit slice, fixes #974Clifford Wolf2019-05-011-0/+2
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Disabled "final loop assignment" featureClifford Wolf2019-04-301-0/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #972 from YosysHQ/clifford/fix968Clifford Wolf2019-04-301-0/+7
| |\ \ | | | | | | | | Add final loop variable assignment when unrolling for-loops
| | * | Add final loop variable assignment when unrolling for-loops, fixes #968Clifford Wolf2019-04-301-0/+7
| | |/ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * / Include filename in "Executing Verilog-2005 frontend" message, fixes #959Clifford Wolf2019-04-301-2/+2
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Move clean from aigerparse to abc9Eddie Hung2019-04-231-2/+0
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* | Tidy upEddie Hung2019-04-221-1/+1
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* | Revert "Temporarily remove 'r' extension"Eddie Hung2019-04-221-0/+18
| | | | | | | | This reverts commit eaf3c247729365cec776e147f380ce59f7dccd4d.
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