Commit message (Collapse) | Author | Age | Files | Lines | ||
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* | | | ast recognize lower case x and z and verific gives upper case | Miodrag Milanovic | 2020-08-30 | 1 | -2/+6 | |
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* | | | Do not check for 1 and 0 only | Miodrag Milanovic | 2020-08-30 | 1 | -6/+0 | |
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* | | | Fix import of VHDL enums | Miodrag Milanovic | 2020-08-30 | 1 | -11/+22 | |
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* | | | Replace "ILANG" with "RTLIL" everywhere. | whitequark | 2020-08-26 | 9 | -91/+106 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility. | |||||
* | | | Add formal apps and template generators | Miodrag Milanovic | 2020-08-26 | 1 | -1/+223 | |
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* | | Merge pull request #2122 from PeterCrozier/struct_array2 | clairexen | 2020-08-19 | 1 | -28/+62 | |
|\ \ | | | | | | | Support 2D bit arrays in structures. Optimise array indexing. | |||||
| * | | Support 2D packed bit arrays in struct/union. | Peter Crozier | 2020-06-09 | 1 | -35/+1 | |
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| * | | Support 2D bit arrays in structures. Optimise array indexing. | Peter Crozier | 2020-06-08 | 1 | -28/+96 | |
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* | | | Merge pull request #2339 from zachjs/display-format-0s | clairexen | 2020-08-18 | 1 | -1/+1 | |
|\ \ \ | | | | | | | | | Allow %0s $display format specifier | |||||
| * | | | Allow %0s $display format specifier | Zachary Snow | 2020-08-09 | 1 | -1/+1 | |
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* | | | Merge pull request #2338 from zachjs/const-branch-finish | clairexen | 2020-08-18 | 1 | -4/+4 | |
|\ \ \ | | | | | | | | | Propagate const_fold through generate blocks and branches | |||||
| * | | | Propagate const_fold through generate blocks and branches | Zachary Snow | 2020-08-09 | 1 | -4/+4 | |
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* | | | Merge pull request #2317 from zachjs/expand-genblock | clairexen | 2020-08-18 | 2 | -42/+83 | |
|\ \ \ | | | | | | | | | Fix generate scoping issues | |||||
| * | | | Fix generate scoping issues | Zachary Snow | 2020-07-31 | 2 | -42/+83 | |
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456 | |||||
* | | | Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into ↵ | Claire Wolf | 2020-08-18 | 1 | -26/+29 | |
|\ \ \ | | | | | | | | | | | | | | | | | | | | | zachjs-const-func-block-var Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
| * | | | Allow blocks with declarations within constant functions | Zachary Snow | 2020-07-25 | 1 | -18/+21 | |
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* | | | | Merge pull request #2281 from zachjs/const-real | clairexen | 2020-08-18 | 1 | -3/+11 | |
|\ \ \ \ | |_|/ / |/| | | | Allow reals as constant function parameters | |||||
| * | | | Allow reals as constant function parameters | Zachary Snow | 2020-07-19 | 1 | -3/+11 | |
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* | | | Clear last error message | Miodrag Milanovic | 2020-07-29 | 1 | -1/+3 | |
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* | | | Merge pull request #2301 from zachjs/for-loop-errors | clairexen | 2020-07-28 | 1 | -17/+19 | |
|\ \ \ | | | | | | | | | Clearer for loop error messages | |||||
| * | | | Clearer for loop error messages | Zachary Snow | 2020-07-25 | 1 | -17/+19 | |
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* / / | Avoid generating wires for function args which are constant | Zachary Snow | 2020-07-24 | 1 | -0/+28 | |
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* | | Treat all bison warnings as errors in verilog front-end | Claire Wolf | 2020-07-15 | 1 | -1/+1 | |
| | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
* | | Use %precedence in verilog_parser.y | Claire Wolf | 2020-07-15 | 1 | -4/+4 | |
| | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
* | | Fix bison warnings for missing %empty | Claire Wolf | 2020-07-15 | 1 | -59/+52 | |
| | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
* | | Run bison with -Wall for verilog front-end | Claire Wolf | 2020-07-15 | 1 | -1/+1 | |
| | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
* | | Merge pull request #2257 from antmicro/fix-conflicts | clairexen | 2020-07-15 | 1 | -9/+10 | |
|\ \ | | | | | | | Restore #2203 and #2244 and fix parser conflicts | |||||
| * | | Add missing semicolons | Kamil Rakoczy | 2020-07-15 | 1 | -5/+5 | |
| | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | |||||
| * | | Fix S/R conflicts | Kamil Rakoczy | 2020-07-10 | 1 | -1/+2 | |
| | | | | | | | | | | | | | | | | | | This commit fixes S/R conflicts introduced by commit 6f9be93. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | |||||
| * | | Fix R/R conflicts | Kamil Rakoczy | 2020-07-10 | 1 | -10/+1 | |
| | | | | | | | | | | | | | | | | | | | | | This commit fixes R/R conflicts introduced by commit 7e83a51. Parameter logic is already defined as part of `param_range_type` rule. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | |||||
| * | | Revert "Revert PRs #2203 and #2244." | Kamil Rakoczy | 2020-07-10 | 1 | -10/+19 | |
| | | | | | | | | | | | | This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a. | |||||
* | | | Add AST_EDGE support to AstNode::detect_latch(), fixes #2241 | Claire Wolf | 2020-07-10 | 1 | -0/+2 | |
|/ / | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
* | | verilog_parser: turn S/R and R/R conflicts into hard errors. | whitequark | 2020-07-09 | 1 | -1/+1 | |
| | | | | | | | | Fixes #2253. | |||||
* | | Revert PRs #2203 and #2244. | whitequark | 2020-07-09 | 1 | -19/+10 | |
| | | | | | | | | | | | | | | | | This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15. This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405. This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3. This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68. This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2. | |||||
* | | Support logic typed parameters | Lukasz Dalek | 2020-07-06 | 1 | -7/+10 | |
| | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> | |||||
* | | Merge pull request #2132 from YosysHQ/eddie/verific_initial | clairexen | 2020-07-02 | 1 | -17/+36 | |
|\ \ | | | | | | | verific: rewrite initial assume/asserts prior to elaboration | |||||
| * | | verific: rewrite initial assume/asserts prior to elaboration | Eddie Hung | 2020-05-15 | 1 | -17/+36 | |
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* | | | Merge pull request #2203 from antmicro/fix-grammar | clairexen | 2020-07-01 | 1 | -4/+10 | |
|\ \ \ | | | | | | | | | Signed and macro grammar update | |||||
| * | | | Parse macro call attached semicolon as empty expression | Lukasz Dalek | 2020-06-26 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> | |||||
| * | | | Fix integer signing grammar | Lukasz Dalek | 2020-06-26 | 1 | -3/+9 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes signed/unsigned grammar in parameters as defined in SV LRM A2.2.1. Example of correct parameters: parameter integer signed i = 0; parameter integer unsigned i = 0; Example of incorrect parameters: parameter signed integer i = 0; parameter unsigned integer i = 0; Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | |||||
* | | | | Merge pull request #2179 from splhack/static-cast | clairexen | 2020-07-01 | 6 | -0/+55 | |
|\ \ \ \ | | | | | | | | | | | Support SystemVerilog Static Cast | |||||
| * | | | | static cast: simplify | Kazuki Sakamoto | 2020-06-19 | 1 | -0/+7 | |
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| * | | | | static cast: support changing size and signedness | Kazuki Sakamoto | 2020-06-19 | 6 | -0/+48 | |
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535 | |||||
* | | | | Merge pull request #2136 from zachjs/master | clairexen | 2020-06-30 | 1 | -1/+5 | |
|\ \ \ \ | | | | | | | | | | | Allow constant function calls in for loops and generate if and case | |||||
| * | | | | Allow constant function calls in for loops and generate if and case | Zachary Snow | 2020-06-29 | 1 | -1/+5 | |
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* | | | | | Update verific API version check | Miodrag Milanovic | 2020-06-30 | 1 | -1/+1 | |
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* | | | | Fix crash in verific frontend | Miodrag Milanovic | 2020-06-26 | 1 | -1/+2 | |
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* | | | | Merge pull request #2188 from antmicro/missing-operators | whitequark | 2020-06-26 | 2 | -2/+49 | |
|\ \ \ \ | | | | | | | | | | | Add logic-assignments operators | |||||
| * | | | | Support missing sub-assign and and-assign operators | Kamil Rakoczy | 2020-06-25 | 2 | -2/+21 | |
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | |||||
| * | | | | Support missing xor-assign operator | Lukasz Dalek | 2020-06-24 | 2 | -1/+10 | |
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> |