iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()	Clifford Wolf	2016-08-21	1	-4/+15
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*	Fixed finish_addr handling in $readmemh/$readmemb	Clifford Wolf	2016-08-20	1	-3/+3
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*	Optimize memory address port width in wreduce and memory_collect, not ↵	Clifford Wolf	2016-08-19	2	-4/+13
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*	Only allow posedge/negedge with 1 bit wide signals	Clifford Wolf	2016-08-10	1	-0/+2
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*	Fixed bug in parsing real constants	Clifford Wolf	2016-08-06	1	-4/+4
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*	Added $anyconst and $aconst	Clifford Wolf	2016-07-27	3	-1/+50
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*	Added "read_verilog -dump_rtlil"	Clifford Wolf	2016-07-27	3	-9/+30
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*	Fixed a verilog parser memory leak	Clifford Wolf	2016-07-25	1	-0/+1
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*	Fixed parsing of empty positional cell ports	Clifford Wolf	2016-07-25	1	-2/+31
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*	No tristate warning message for "read_verilog -lib"	Clifford Wolf	2016-07-23	3	-8/+11
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*	Using $initstate in "initial assume" and "initial assert"	Clifford Wolf	2016-07-21	1	-1/+6
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*	Added $initstate cell type and vlog function	Clifford Wolf	2016-07-21	2	-0/+26
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*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	6	-12/+16
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*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	6	-8/+25
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*	Fixed mem assignment in left-hand-side concatenation	Clifford Wolf	2016-07-08	1	-0/+44
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*	Allow defining input ports as "input logic" in SystemVerilog	Ruben Undheim	2016-06-20	1	-2/+2
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*	Merge branch 'sv_packages' of https://github.com/rubund/yosys	Clifford Wolf	2016-06-19	5	-1/+49
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\| *	A few modifications after pull request comments	Ruben Undheim	2016-06-18	1	-2/+2
\| \| \| \| \| \| \| \| \| \|	- Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h
\| *	Added support for SystemVerilog packages with localparam definitions	Ruben Undheim	2016-06-18	5	-1/+49
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* \|	Added "read_blif -sop"	Clifford Wolf	2016-06-18	1	-5/+10
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*	Added $sop cell type and "abc -sop"	Clifford Wolf	2016-06-17	2	-24/+80
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*	Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}	Clifford Wolf	2016-05-27	1	-0/+11
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*	Fixed access-after-delete bug in mem2reg code	Clifford Wolf	2016-05-27	2	-6/+23
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*	fixed typos in error messages	Clifford Wolf	2016-05-27	1	-3/+3
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*	Small improvements in Verilog front-end docs	Clifford Wolf	2016-05-20	1	-0/+3
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*	Include <cmath> in yosys.h	Clifford Wolf	2016-05-08	1	-9/+0
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*	Added support for "active high" and "active low" latches in BLIF front-end	Clifford Wolf	2016-04-22	1	-0/+4
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*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	7	-8/+8
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*	Fixed handling of parameters and const functions in casex/casez pattern	Clifford Wolf	2016-04-21	5	-8/+37
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*	Do not set "nosync" on task outputs, fixes #134	Clifford Wolf	2016-03-24	1	-1/+2
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*	Added support for $stop system task	Clifford Wolf	2016-03-21	1	-5/+5
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*	Added $display %m support, fixed mem leak in $display, fixes #128	Clifford Wolf	2016-03-19	1	-20/+44
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*	Fixed localparam signdness, fixes #127	Clifford Wolf	2016-03-18	1	-1/+1
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*	Set "nosync" attribute on internal task/function wires	Clifford Wolf	2016-03-18	1	-0/+1
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*	Fixed Verilog parser fix and more similar improvements	Clifford Wolf	2016-03-15	1	-18/+9
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*	Use left-recursive rule for cell_port_list in Verilog parser.	Andrew Becker	2016-03-15	1	-6/+10
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*	Fixed typos in verilog_defaults help message	Clifford Wolf	2016-03-10	1	-3/+3
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*	Fixed BLIF parser for empty port assignments	Clifford Wolf	2016-02-24	1	-2/+2
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*	Fixed some visual studio warnings	Clifford Wolf	2016-02-13	3	-4/+4
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*	Support for more Verific primitives (patch I got per email)	Clifford Wolf	2016-02-13	1	-1/+31
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*	Bugfix in Verific front-end	Clifford Wolf	2016-02-03	1	-2/+5
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*	Updated verific build instructions	Clifford Wolf	2016-02-02	1	-2/+0
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*	Added addBufGate module method	Clifford Wolf	2016-02-02	1	-0/+5
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*	genrtlil: avoid converting SigSpec to set<SigBit> when going through ↵	Rick Altherr	2016-01-31	1	-3/+3
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*	Various improvements in BLIF front-end	Clifford Wolf	2015-12-20	2	-41/+86
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*	Fixed oom bug in ilang parser	Clifford Wolf	2015-11-29	1	-2/+2
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*	Fixed performance bug in ilang parser	Clifford Wolf	2015-11-27	1	-6/+12
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*	Added PRIM_DLATCHRS support to verific front-end	Clifford Wolf	2015-11-24	1	-0/+10
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*	Fixed handling of re-declarations of wires in tasks and functions	Clifford Wolf	2015-11-23	1	-7/+26
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*	Fixed performance bug in Verific importer	Clifford Wolf	2015-11-16	1	-10/+12
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