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| * Remove unnecessary std::getline() for ASCIIEddie Hung2019-06-071-3/+0
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| * Fix read_aiger -- create zero driver, fix init width, parse 'b'Eddie Hung2019-06-072-13/+52
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| * Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-073-46/+34
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-076-5/+64
| |\ | | | | | | | | | clifford/pr983
| | * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-036-5/+64
| | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
| * | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-071-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-071-1/+10
| |\ \ | | | | | | | | | | | | into tux3-implicit_named_connection
| | * | SystemVerilog support for implicit named port connectionstux32019-06-061-9/+17
| | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
| * | | Merge pull request #1060 from antmicro/parsing_attr_on_port_connClifford Wolf2019-06-061-10/+14
| |\ \ \ | | |/ / | |/| | Added support for parsing attributes on port connections.
| | * | Fixed memory leak.Maciej Kurc2019-06-051-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| | * | Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
| | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | Only support Symbiotic EDA flavored VerificClifford Wolf2019-06-021-0/+8
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ↵Clifford Wolf2019-05-301-0/+3
| | | | | | | | | | | | | | | | | | fixes #1055 Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'master' into wandworStefan Biereigel2019-05-275-14/+47
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| | * \ Merge pull request #1044 from mmicko/invalid_width_rangeClifford Wolf2019-05-271-1/+2
| | |\ \ | | | | | | | | | | Give error instead of asserting for invalid range, fixes #947
| | | * | Give error instead of asserting for invalid range, fixes #947Miodrag Milanovic2019-05-271-1/+2
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| | * | | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-275-13/+45
| | |/ / | | | | | | | | | | | | Includes work from @sumit0190 and @AaronKel
| * | | remove leftovers from ast data structuresStefan Biereigel2019-05-272-4/+0
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| * | | move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-97/+14
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| * | | fix assignment of non-wiresStefan Biereigel2019-05-231-16/+19
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| * | | fix indentation across filesStefan Biereigel2019-05-234-63/+83
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| * | | implementation for assignments workingStefan Biereigel2019-05-233-14/+83
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| * | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-233-2/+10
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| * | Rename labelEddie Hung2019-05-211-6/+5
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| * | Try againEddie Hung2019-05-211-4/+10
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| * | Fix warningEddie Hung2019-05-211-3/+2
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| * | Read bigger Verilog files.Kaj Tuomi2019-05-181-1/+1
| | | | | | | | | | | | Hit parser limit with 3M gate design. This commit fix it.
| * | Merge pull request #1013 from antmicro/parameter_attributesClifford Wolf2019-05-161-2/+2
| |\ \ | | | | | | | | Support for attributes on parameters and localparams for Verilog frontend
| | * | Added support for parsing attributes on parameters in Verilog frontent. ↵Maciej Kurc2019-05-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Content of those attributes is ignored. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-142-2/+18
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| * | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-068-35/+366
| |\ \ | | | | | | | | Add specify parser
| | * | Add "real" keyword to ilang formatClifford Wolf2019-05-062-1/+8
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-062-2/+10
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| | * | | Improve write_verilog specify supportClifford Wolf2019-05-041-0/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-033-2/+14
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| | * | | | Improve $specrule interfaceClifford Wolf2019-04-232-9/+19
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Improve $specrule interfaceClifford Wolf2019-04-231-20/+18
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-234-4/+86
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Allow $specify[23] cells in blackbox modulesClifford Wolf2019-04-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Checking and fixing specify cells in genRTLILClifford Wolf2019-04-231-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Add specify parserClifford Wolf2019-04-234-33/+243
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-061-2/+0
| |\ \ \ \ \ | | | | | | | | | | | | | | Re-enable "final loop assignment" feature and fix opt_clean warnings
| | * \ \ \ \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-065-4/+15
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| | * | | | | | Re-enable "final loop assignment" featureClifford Wolf2019-05-011-2/+0
| | | |_|_|_|/ | | |/| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-062-26/+71
| |\ \ \ \ \ \ | | |_|/ / / / | |/| | | | | Improve verific -chparam and add hierarchy -chparam
| | * | | | | For hier_tree::Elaborate() also include SV root modules (bind)Eddie Hung2019-05-031-23/+36
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| | * | | | | Fix verific_parameters construction, use attribute to mark top netlistsEddie Hung2019-05-032-8/+12
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| | * | | | | WIP -chparam support for hierarchy when verificEddie Hung2019-05-032-12/+17
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