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* | | Do not check for 1 and 0 onlyMiodrag Milanovic2020-08-301-6/+0
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* | | Fix import of VHDL enumsMiodrag Milanovic2020-08-301-11/+22
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* | | Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-269-91/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* | | Add formal apps and template generatorsMiodrag Milanovic2020-08-261-1/+223
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* | Merge pull request #2122 from PeterCrozier/struct_array2clairexen2020-08-191-28/+62
|\ \ | | | | | | Support 2D bit arrays in structures. Optimise array indexing.
| * | Support 2D packed bit arrays in struct/union.Peter Crozier2020-06-091-35/+1
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| * | Support 2D bit arrays in structures. Optimise array indexing.Peter Crozier2020-06-081-28/+96
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* | | Merge pull request #2339 from zachjs/display-format-0sclairexen2020-08-181-1/+1
|\ \ \ | | | | | | | | Allow %0s $display format specifier
| * | | Allow %0s $display format specifierZachary Snow2020-08-091-1/+1
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* | | Merge pull request #2338 from zachjs/const-branch-finishclairexen2020-08-181-4/+4
|\ \ \ | | | | | | | | Propagate const_fold through generate blocks and branches
| * | | Propagate const_fold through generate blocks and branchesZachary Snow2020-08-091-4/+4
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* | | Merge pull request #2317 from zachjs/expand-genblockclairexen2020-08-182-42/+83
|\ \ \ | | | | | | | | Fix generate scoping issues
| * | | Fix generate scoping issuesZachary Snow2020-07-312-42/+83
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
* | | Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into ↵Claire Wolf2020-08-181-26/+29
|\ \ \ | | | | | | | | | | | | | | | | | | | | zachjs-const-func-block-var Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Allow blocks with declarations within constant functionsZachary Snow2020-07-251-18/+21
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* | | | Merge pull request #2281 from zachjs/const-realclairexen2020-08-181-3/+11
|\ \ \ \ | |_|/ / |/| | | Allow reals as constant function parameters
| * | | Allow reals as constant function parametersZachary Snow2020-07-191-3/+11
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* | | Clear last error messageMiodrag Milanovic2020-07-291-1/+3
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* | | Merge pull request #2301 from zachjs/for-loop-errorsclairexen2020-07-281-17/+19
|\ \ \ | | | | | | | | Clearer for loop error messages
| * | | Clearer for loop error messagesZachary Snow2020-07-251-17/+19
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* / / Avoid generating wires for function args which are constantZachary Snow2020-07-241-0/+28
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* | Treat all bison warnings as errors in verilog front-endClaire Wolf2020-07-151-1/+1
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Use %precedence in verilog_parser.yClaire Wolf2020-07-151-4/+4
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Fix bison warnings for missing %emptyClaire Wolf2020-07-151-59/+52
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Run bison with -Wall for verilog front-endClaire Wolf2020-07-151-1/+1
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Merge pull request #2257 from antmicro/fix-conflictsclairexen2020-07-151-9/+10
|\ \ | | | | | | Restore #2203 and #2244 and fix parser conflicts
| * | Add missing semicolonsKamil Rakoczy2020-07-151-5/+5
| | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | Fix S/R conflictsKamil Rakoczy2020-07-101-1/+2
| | | | | | | | | | | | | | | | | | This commit fixes S/R conflicts introduced by commit 6f9be93. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | Fix R/R conflictsKamil Rakoczy2020-07-101-10/+1
| | | | | | | | | | | | | | | | | | | | | This commit fixes R/R conflicts introduced by commit 7e83a51. Parameter logic is already defined as part of `param_range_type` rule. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | Revert "Revert PRs #2203 and #2244."Kamil Rakoczy2020-07-101-10/+19
| | | | | | | | | | | | This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
* | | Add AST_EDGE support to AstNode::detect_latch(), fixes #2241Claire Wolf2020-07-101-0/+2
|/ / | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | verilog_parser: turn S/R and R/R conflicts into hard errors.whitequark2020-07-091-1/+1
| | | | | | | | Fixes #2253.
* | Revert PRs #2203 and #2244.whitequark2020-07-091-19/+10
| | | | | | | | | | | | | | | | This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15. This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405. This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3. This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68. This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
* | Support logic typed parametersLukasz Dalek2020-07-061-7/+10
| | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | Merge pull request #2132 from YosysHQ/eddie/verific_initialclairexen2020-07-021-17/+36
|\ \ | | | | | | verific: rewrite initial assume/asserts prior to elaboration
| * | verific: rewrite initial assume/asserts prior to elaborationEddie Hung2020-05-151-17/+36
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* | | Merge pull request #2203 from antmicro/fix-grammarclairexen2020-07-011-4/+10
|\ \ \ | | | | | | | | Signed and macro grammar update
| * | | Parse macro call attached semicolon as empty expressionLukasz Dalek2020-06-261-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * | | Fix integer signing grammarLukasz Dalek2020-06-261-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes signed/unsigned grammar in parameters as defined in SV LRM A2.2.1. Example of correct parameters: parameter integer signed i = 0; parameter integer unsigned i = 0; Example of incorrect parameters: parameter signed integer i = 0; parameter unsigned integer i = 0; Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | | | Merge pull request #2179 from splhack/static-castclairexen2020-07-016-0/+55
|\ \ \ \ | | | | | | | | | | Support SystemVerilog Static Cast
| * | | | static cast: simplifyKazuki Sakamoto2020-06-191-0/+7
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| * | | | static cast: support changing size and signednessKazuki Sakamoto2020-06-196-0/+48
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* | | | Merge pull request #2136 from zachjs/masterclairexen2020-06-301-1/+5
|\ \ \ \ | | | | | | | | | | Allow constant function calls in for loops and generate if and case
| * | | | Allow constant function calls in for loops and generate if and caseZachary Snow2020-06-291-1/+5
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* | | | | Update verific API version checkMiodrag Milanovic2020-06-301-1/+1
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* | | | Fix crash in verific frontendMiodrag Milanovic2020-06-261-1/+2
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* | | | Merge pull request #2188 from antmicro/missing-operatorswhitequark2020-06-262-2/+49
|\ \ \ \ | | | | | | | | | | Add logic-assignments operators
| * | | | Support missing sub-assign and and-assign operatorsKamil Rakoczy2020-06-252-2/+21
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | Support missing xor-assign operatorLukasz Dalek2020-06-242-1/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * | | | Add plus-assignment operatorKamil Rakoczy2020-06-242-1/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 14:02:38 +0000