iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add flooring division operator	Xiretza	2020-05-28	1	-1/+1
\| \| \| \| \| \| \| \| \| \|	The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
*	Add flooring modulo operator	Xiretza	2020-05-28	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \|	The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-49/+35
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*	Use more ID::{A,B,Y,blackbox,whitebox}	Eddie Hung	2019-08-15	1	-7/+7
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*	Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)	Clifford Wolf	2019-08-11	1	-21/+21
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()	Clifford Wolf	2016-07-25	1	-1/+1
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*	Improvements in CellEdgesDatabase	Clifford Wolf	2016-07-24	1	-10/+131
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*	Added CellEdgesDatabase API	Clifford Wolf	2016-07-24	1	-0/+88