| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundef | Jannis Harder | 2023-01-11 | 1 | -0/+1 |
| | | | | | | | | | This adds the xprop_decoder attribute to bwmuxes that drive the original unencoded signals. Setundef is changed to ignore the x inputs of these bwmuxes, so that they survive the prep script of SBY's formal flow. This is required to make simulation (via sim) using the prep model show the decoded x signals instead of 0/1 values made up by the solver. | ||||
| * | formalff: Set new replaced_by_gclk attribute on removed dff's clks | Jannis Harder | 2022-08-16 | 1 | -0/+1 |
| | | | | | | | This attribute can be used by formal backends to indicate which clocks were mapped to the global clock. Update the btor and smt2 backend which already handle clock inputs to understand this attribute. | ||||
| * | smt2: Add smtlib2_comb_expr attribute to allow user-selected smtlib2 expressions | Jacob Lifshay | 2022-06-02 | 1 | -0/+2 |
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| * | memory_dff: Add support for no_rw_check attribute. | Marcelina Kościelnicka | 2022-06-02 | 1 | -0/+1 |
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| * | Add memory_libmap pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -0/+12 |
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| * | sta: very crude static timing analysis pass | Lofty | 2021-11-25 | 1 | -0/+1 |
| | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com> | ||||
| * | verilog: use derived module info to elaborate cell connections | Zachary Snow | 2021-10-25 | 1 | -0/+1 |
| | | | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change | ||||
| * | Add $aldff and $aldffe: flip-flops with async load. | Marcelina Kościelnicka | 2021-10-02 | 1 | -0/+3 |
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| * | Add v2 memory cells. | Marcelina Kościelnicka | 2021-08-11 | 1 | -0/+17 |
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| * | techmap: Add _TECHMAP_CELLNAME_ special parameter. | Marcelina Kościelnicka | 2020-07-21 | 1 | -0/+1 |
| | | | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells. | ||||
| * | Add new builtin FF types | Marcelina Kościelnicka | 2020-06-23 | 1 | -0/+3 |
| | | | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits). | ||||
| * | Merge pull request #1862 from boqwxp/cleanup_techmap | clairexen | 2020-05-31 | 1 | -0/+1 |
| |\ | | | | | Clean up `passes/techmap/techmap.cc` | ||||
| | * | techmap: prefix special wires with backslash for use as IdString | Eddie Hung | 2020-05-14 | 1 | -0/+1 |
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| * | | Add force_downto and force_upto wire attributes. | Marcelina Kościelnicka | 2020-05-19 | 1 | -0/+2 |
| | | | | | | | | | Fixes #2058. | ||||
| * | | abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ | Eddie Hung | 2020-05-14 | 1 | -1/+1 |
| | | | | | | | | | instead of moving them to $__ prefix | ||||
| * | | abc9_ops: fix bypass boxes using (* abc9_bypass *) | Eddie Hung | 2020-05-14 | 1 | -2/+1 |
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| * | | Merge pull request #2005 from YosysHQ/claire/fix1990 | Claire Wolf | 2020-05-07 | 1 | -0/+1 |
| |\ \ | |/ |/| | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset | ||||
| | * | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵ | Claire Wolf | 2020-05-02 | 1 | -0/+1 |
| | | | | | | | | | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
| * | | frontend: cleanup to use more ID::*, more dict<> instead of map<> | Eddie Hung | 2020-05-04 | 1 | -0/+3 |
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| * | Merge pull request #1992 from YosysHQ/eddie/bugpoint_help | Eddie Hung | 2020-04-27 | 1 | -0/+1 |
| |\ | | | | | bugpoint: improve help text | ||||
| | * | bugpoint: (* keep *) to (* bugpoint_keep *); also apply to modules/cells | Eddie Hung | 2020-04-24 | 1 | -0/+1 |
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| * | | verific: do not assert if wire not found; warn instead | Eddie Hung | 2020-04-23 | 1 | -0/+1 |
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| * | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -7/+193 |
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| * | kernel: Use constids.inc for global/constant IdStrings | Eddie Hung | 2020-04-02 | 1 | -0/+27 |
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