iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Handle possible non-memory indexed data	Miodrag Milanovic	2022-05-06	1	-8/+10
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*	map memory location to wire value, if memory is converted to FFs	Miodrag Milanovic	2022-05-04	1	-0/+4
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*	Start restoring memory state from VCD/FST	Miodrag Milanovic	2022-05-04	1	-1/+31
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*	Ignore change on last edge	Miodrag Milanovic	2022-04-22	1	-4/+5
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*	Proper scope naming from FST	Miodrag Milanovic	2022-03-30	1	-8/+4
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*	More verbose warnings	Miodrag Milanovic	2022-03-18	1	-1/+2
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*	Recognize registers and set initial state for them in tb	Miodrag Milanovic	2022-03-16	1	-0/+1
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*	VCD reader support by using external tool	Miodrag Milanovic	2022-02-28	1	-0/+19
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*	Fix for last clock edge data	Miodrag Milanovic	2022-02-25	1	-0/+1
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*	Changed error message	Miodrag Milanovic	2022-02-18	1	-1/+1
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*	Add support for various ff/latch cells simulation	Miodrag Milanovic	2022-02-16	1	-98/+43
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*	Error detection for co-simulation	Miodrag Milanovic	2022-02-04	1	-0/+2
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*	bug fix and cleanups	Miodrag Milanovic	2022-02-04	1	-1/+1
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*	Cleanup	Miodrag Milanovic	2022-01-31	1	-1/+0
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*	Display simulation time data	Miodrag Milanovic	2022-01-31	1	-1/+21
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*	ignore not found private signals	Miodrag Milanovic	2022-01-28	1	-2/+1
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*	preserve VCD mangled names	Miodrag Milanovic	2022-01-28	1	-1/+3
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*	detect edges even when x	Miodrag Milanovic	2022-01-28	1	-2/+2
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*	cleanup	Miodrag Milanovic	2022-01-28	1	-13/+1
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*	Do actual compare	Miodrag Milanovic	2022-01-28	1	-65/+41
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*	Add more options and time handling	Miodrag Milanovic	2022-01-28	1	-0/+1
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*	Add fstdata helper class	Miodrag Milanovic	2022-01-26	1	-0/+265