iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fixed issue when using a python plugin in the yosys shell	Benedikt Tutzer	2018-08-20	1	-4/+7
\|
*	Python Passes can now be added with the -m option or with the plugin ↵	Benedikt Tutzer	2018-08-16	1	-1/+65
\| \| \| \|	command. There are still issues when run in shell mode, but they can be used just fine in a python script
*	Added Wrappers for:	Benedikt Tutzer	2018-08-13	1	-138/+2881
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	-IdString -Const -CaseRule -SwitchRule -SyncRule -Process -SigChunk -SigBit -SigSpec With all their member functions as well as the remaining member functions for Cell, Wire, Module and Design and static functions of rtlil.h
*	Saving id and pointer to c++ object. Object is valid only if both id and ↵	Benedikt Tutzer	2018-08-01	1	-8/+29
\| \| \| \|	pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more
*	Setup is called automatically when the module is loaded, shutdown when ↵	Benedikt Tutzer	2018-08-01	1	-16/+19
\| \| \| \|	python exits
*	Cleaned up comments	Benedikt Tutzer	2018-08-01	1	-9/+3
\|
*	Added Monitor class that can monitor all changes in a Design or in a Module	Benedikt Tutzer	2018-07-10	1	-0/+119
\|
*	commands can now be run on arbitrary designs, not only on the active one	Benedikt Tutzer	2018-07-09	1	-0/+10
\|
*	multiple designs can now exist independent from each other. ↵	Benedikt Tutzer	2018-07-09	1	-45/+47
\| \| \| \|	Cells/Wires/Modules can now move to a different parent without referencing issues
*	Introduced namespace and removed class-prefixes to increase readability	Benedikt Tutzer	2018-06-28	1	-163/+165
\|
*	changed references from hash-ids to IdString names	Benedikt Tutzer	2018-06-28	1	-64/+32
\|
*	added wrappers for Design, Modules, Cells and Wires	Benedikt Tutzer	2018-06-25	1	-0/+244