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* kernel/mem: Only use FF init in read-first emu for mem with initMarcelina Kościelnicka2022-03-281-1/+4
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* Add some more reserve calls to RTLIL::ConstNotAFile2022-03-251-0/+5
| | | | This results in a slight ~0.22% total speedup synthesizing vexriscv
* More verbose warningsMiodrag Milanovic2022-03-181-1/+2
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* Recognize registers and set initial state for them in tbMiodrag Milanovic2022-03-162-0/+2
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* VCD reader support by using external toolMiodrag Milanovic2022-02-282-0/+20
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* Fix for last clock edge dataMiodrag Milanovic2022-02-251-0/+1
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* Changed error messageMiodrag Milanovic2022-02-181-1/+1
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* Add support for various ff/latch cells simulationMiodrag Milanovic2022-02-162-109/+54
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* Merge branch 'master' into clk2ff-better-namesClaire Xen2022-02-1140-673/+4431
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| * Merge pull request #3185 from YosysHQ/micko/co_simMiodrag Milanović2022-02-072-0/+333
| |\ | | | | | | Add co-simulation in sim pass
| | * Error detection for co-simulationMiodrag Milanovic2022-02-041-0/+2
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| | * bug fix and cleanupsMiodrag Milanovic2022-02-041-1/+1
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| | * CleanupMiodrag Milanovic2022-01-311-1/+0
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| | * Display simulation time dataMiodrag Milanovic2022-01-312-1/+23
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| | * ignore not found private signalsMiodrag Milanovic2022-01-281-2/+1
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| | * preserve VCD mangled namesMiodrag Milanovic2022-01-281-1/+3
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| | * detect edges even when xMiodrag Milanovic2022-01-281-2/+2
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| | * cleanupMiodrag Milanovic2022-01-282-14/+1
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| | * Do actual compareMiodrag Milanovic2022-01-282-72/+47
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| | * Add more options and time handlingMiodrag Milanovic2022-01-282-0/+3
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| | * Fix tabs/spacesMiodrag Milanovic2022-01-261-31/+31
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| | * Add fstdata helper classMiodrag Milanovic2022-01-262-0/+344
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| * | Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-288-20/+291
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| * | kernel/mem: Add read-first semantic emulation code.Marcelina Kościelnicka2022-01-282-0/+116
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| * | kernel/mem: Add functions to emulate read port enable/init/reset signals.Marcelina Kościelnicka2022-01-272-0/+226
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| * logger: fix unmatched expected warnings and errorsZachary Snow2022-01-041-11/+11
| | | | | | | | | | | | | | | | - Prevent unmatched expected error patterns from self-matching - Prevent infinite recursion on unmatched expected warnings - Always print the error message for unmatched error patterns - Add test coverage for all unmatched message types - Add test coverage for excess matched logs and warnings
| * Merge pull request #3111 from whitequark/issue-3110Catherine2021-12-141-1/+2
| |\ | | | | | | Fix null pointer dereference after failing to extract DFF from memory
| | * Fix null pointer dereference after failing to extract DFF from memory.Catherine2021-12-141-1/+2
| | | | | | | | | | | | Fixes #3110.
| * | Hotfix for run_shell auto-detectionClaire Xenia Wolf2021-12-141-0/+3
| |/ | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Fix unused param warning with ENABLE_NDEBUG.Marcelina Kościelnicka2021-12-121-1/+1
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| * Added "yosys -r <topmodule>"Claire Xenia Wolf2021-12-103-28/+35
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Use "read" command to parse HDL files from Yosys command-lineClaire Xenia Wolf2021-12-091-4/+8
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * sta: very crude static timing analysis passLofty2021-11-254-17/+64
| | | | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
| * Make it work on allMiodrag Milanovic2021-11-051-3/+1
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| * Removed semicolon from macroMiodrag Milanovic2021-11-051-1/+1
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| * dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-272-7/+202
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| * verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-253-0/+7
| | | | | | | | | | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
| * Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-252-3/+3
| | | | | | | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
| * Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-211-2/+2
| | | | | | | | Also fixes some completely broken code in extract_reduce.
| * Fix a regression from #3035.Marcelina Kościelnicka2021-10-081-1/+1
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| * FfData: some refactoring.Marcelina Kościelnicka2021-10-074-453/+604
| | | | | | | | | | | | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
| * Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-021-2/+41
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| * kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-024-152/+275
| | | | | | | | | | | | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
| * Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-024-0/+130
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| * simplemap: refactor to use FfData.Marcelina Kościelnicka2021-10-021-3/+6
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| * Add additional check to SigSpecClaire Xenia Wolf2021-09-102-6/+14
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * kernel/mem: Remove old parameter when upgrading $mem to $mem_v2.Marcelina Kościelnicka2021-08-161-0/+1
| | | | | | | | Fixes #2967.
| * Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-134-1/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code now takes the AST nodes of type AST_BIND and generates a representation in the RTLIL for them. This is a little tricky, because a binding of the form: bind baz foo_t foo_i (.arg (1 + bar)); means "make an instance of foo_t called foo_i, instantiate it inside baz and connect the port arg to the result of the expression 1+bar". Of course, 1+bar needs a cell for the addition. Where should that cell live? With this patch, the Binding structure that represents the construct is itself an AST::AstModule module. This lets us put the adder cell inside it. We'll pull the contents out and plonk them into 'baz' when we actually do the binding operation as part of the hierarchy pass. Of course, we don't want RTLIL::Binding to contain an AST::AstModule (since kernel code shouldn't depend on a frontend), so we define RTLIL::Binding as an abstract base class and put the AST-specific code into an AST::Binding subclass. This is analogous to the AST::AstModule class.
| * logger: Add -check-expected subcommand.Marcelina Kościelnicka2021-08-121-5/+5
| | | | | | | | | | This allows us to have multiple "expect this warning" calls in a single long script, covering only as many passes as necessary.
| * Add v2 memory cells.Marcelina Kościelnicka2021-08-114-137/+312
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