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* Exposed generator script to make-processBenedikt Tutzer2018-09-192-3888/+2
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* added functions whose definitions are split over multiple linesBenedikt Tutzer2018-08-231-0/+60
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* added default yosys license textBenedikt Tutzer2018-08-231-0/+19
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* Fixed segfault / multiple free issue with listsBenedikt Tutzer2018-08-231-26/+38
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* Do not pass heap object to Python. This way they should be completely ↵Benedikt Tutzer2018-08-221-323/+337
| | | | managed by Python and destroyed when out of scope. Also, the file in which a function/struct was found is added to the comment before the function
* Fixed IdentationBenedikt Tutzer2018-08-221-189/+188
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* Wrapped functions that use unsigned int or type_t as typesBenedikt Tutzer2018-08-211-7/+127
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* added operators <, == and !=Benedikt Tutzer2018-08-211-0/+45
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* Added previousely missed functionsBenedikt Tutzer2018-08-211-1/+445
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* Deleted duplicate DestructorBenedikt Tutzer2018-08-211-1/+0
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* added some checks if python is enabled to make sure everything compiles if ↵Benedikt Tutzer2018-08-204-7/+8
| | | | python is disabled in the makefile
* The share directory cannot be searched when used as a Python library, only ↵Benedikt Tutzer2018-08-202-1/+8
| | | | in shell mode
* Python passes are now looked for in share/plugins and can be added by ↵Benedikt Tutzer2018-08-201-4/+1
| | | | specifying a relative or absolute path
* Fixed issue when using a python plugin in the yosys shellBenedikt Tutzer2018-08-203-4/+28
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* Python Passes can now be added with the -m option or with the plugin ↵Benedikt Tutzer2018-08-163-1/+96
| | | | command. There are still issues when run in shell mode, but they can be used just fine in a python script
* Added Wrappers for:Benedikt Tutzer2018-08-133-142/+2923
| | | | | | | | | | | | | | | -IdString -Const -CaseRule -SwitchRule -SyncRule -Process -SigChunk -SigBit -SigSpec With all their member functions as well as the remaining member functions for Cell, Wire, Module and Design and static functions of rtlil.h
* Saving id and pointer to c++ object. Object is valid only if both id and ↵Benedikt Tutzer2018-08-011-8/+29
| | | | pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more
* Setup is called automatically when the module is loaded, shutdown when ↵Benedikt Tutzer2018-08-011-16/+19
| | | | python exits
* Cleaned up commentsBenedikt Tutzer2018-08-011-9/+3
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* Added Monitor class that can monitor all changes in a Design or in a ModuleBenedikt Tutzer2018-07-101-0/+119
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* added destructors for wires and cellsBenedikt Tutzer2018-07-102-1/+16
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* removed debug outputBenedikt Tutzer2018-07-091-1/+0
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* commands can now be run on arbitrary designs, not only on the active oneBenedikt Tutzer2018-07-091-0/+10
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* multiple designs can now exist independent from each other. ↵Benedikt Tutzer2018-07-093-45/+118
| | | | Cells/Wires/Modules can now move to a different parent without referencing issues
* Introduced namespace and removed class-prefixes to increase readabilityBenedikt Tutzer2018-06-281-163/+165
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* changed references from hash-ids to IdString namesBenedikt Tutzer2018-06-281-64/+32
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* added wrappers for Design, Modules, Cells and WiresBenedikt Tutzer2018-06-251-0/+244
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* Modify emscripten main to mount nodefs and to run arg as a scriptRobert Ou2018-05-181-1/+18
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* Fix reading techlibs under emscriptenRobert Ou2018-05-181-1/+1
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* Add "#ifdef __FreeBSD__"Christian Krämer2018-05-134-8/+51
| | | | (Re-commit e3575a8 with corrected author field)
* Revert "Add "#ifdef __FreeBSD__""Clifford Wolf2018-05-134-51/+8
| | | | This reverts commit e3575a86c525f2511902e7022893c3923ba8093e.
* Add "#ifdef __FreeBSD__"Johnny Sorocil2018-05-054-8/+51
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* Add "yosys -e regex" for turning warnings into errorsClifford Wolf2018-05-043-4/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Set stack size to at least 128 MB (large stack needed for parsing huge ↵Clifford Wolf2018-03-271-0/+13
| | | | | | expressions) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Rename rename to renamesEdmond Cote2018-03-201-3/+5
| | | Create TCL alias for rename command. Using renames. Following the same convention as proc -> procs.
* Harmonize uses of _WIN32 macroLarry Doolittle2018-03-111-1/+1
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* Improve handling of warning messagesClifford Wolf2018-03-043-12/+42
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update copyright headerClifford Wolf2018-03-041-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $allconst and $allseq cell typesClifford Wolf2018-02-233-1/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Do not create deep backtraces unless in ENABLE_DEBUG modeClifford Wolf2018-02-031-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for "yosys -E"Clifford Wolf2018-01-074-2/+36
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-052-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add RTLIL::Const::is_fully_ones()Clifford Wolf2017-12-142-0/+12
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* Add SigSpec::is_fully_ones()Clifford Wolf2017-12-142-0/+16
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* Use quote includes for yosys.hKevin Kiningham2017-12-132-2/+2
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* Add support for editline as replacement for readlineClifford Wolf2017-11-082-10/+29
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* Add src arguments to all cell creator helper functionsClifford Wolf2017-09-092-209/+244
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* Update more stuff to use get_src_attribute() and set_src_attribute()Clifford Wolf2017-09-011-1/+1
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* Merge remote-tracking branch 'upstream/master'Jason Lowdermilk2017-08-302-0/+20
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| * Add {get,set}_src_attribute() methods on RTLIL::AttrObjectClifford Wolf2017-08-302-0/+20
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