| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | More use of IdString::in() | Eddie Hung | 2019-08-15 | 1 | -1/+1 |
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| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
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| * | Renamed hashmap.h to hashlib.h, some related improvements | Clifford Wolf | 2014-12-28 | 1 | -2/+2 |
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| * | More hashtable finetuning | Clifford Wolf | 2014-12-27 | 1 | -2/+2 |
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| * | Replaced std::unordered_set (nodict) with Yosys::pool | Clifford Wolf | 2014-12-26 | 1 | -4/+4 |
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| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -4/+4 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -3/+5 |
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| * | Preparations for RTLIL::IdString redesign: cleanup of existing code | Clifford Wolf | 2014-08-02 | 1 | -3/+3 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
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| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
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| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -30/+5 |
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| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -5/+4 |
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| * | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 | 1 | -2/+3 |
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| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵ | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
| | | | | | created interim RTLIL::SigSpec::chunks_rw() | ||||
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
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| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
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| * | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 | 1 | -1/+1 |
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| * | Added delete {-input|-output|-port} | Clifford Wolf | 2014-02-09 | 1 | -5/+36 |
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| * | Bugfix in delete command | Clifford Wolf | 2014-02-09 | 1 | -1/+3 |
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| * | Added delete command | Clifford Wolf | 2014-02-02 | 1 | -0/+134 |
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