| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Tweak default gate costs, cleanup "stat -tech cmos" | Clifford Wolf | 2019-08-07 | 1 | -16/+6 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 1 | -0/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "stat -tech cmos" | Clifford Wolf | 2019-07-20 | 1 | -2/+29 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix typo | Clifford Wolf | 2019-06-20 | 1 | -2/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "stat -tech xilinx" | Clifford Wolf | 2019-05-11 | 1 | -3/+73 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Include module name for area summary stats | Edmond Cote | 2018-06-18 | 1 | -4/+4 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PR prints the name of the module when displaying the final area count. Pros: - Easier for the user to `grep` for area information about a specific module Cons: - Arguably more verbose, less "pretty" than author desires Verification: ~~~~ 30c30 < Chip area for this module: 20616.349000 --- > Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000 70c70 < Chip area for this module: 88.697700 --- > Chip area for module '\picorv32_axi_adapter': 88.697700 102c102 < Chip area for this module: 20705.046700 --- > Chip area for top module '\picorv32_axi': 20705.046700 ~~~~ | ||||
| * | Add support for "yosys -E" | Clifford Wolf | 2018-01-07 | 1 | -0/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add $alu to list of supported cells for "stat -width" | Clifford Wolf | 2017-07-14 | 1 | -1/+1 |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
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| * | Added "stat -liberty" for calculating chip area | Clifford Wolf | 2016-02-04 | 1 | -6/+60 |
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| * | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -1/+1 |
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| * | improvement in "stat" | Clifford Wolf | 2015-10-24 | 1 | -1/+1 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
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| * | Fixed "stat" handling of blackbox modules | Clifford Wolf | 2015-02-14 | 1 | -9/+6 |
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| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -5/+5 |
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| * | sort cell types in "stat" output by name | Clifford Wolf | 2014-10-03 | 1 | -2/+2 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -113/+114 |
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| * | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 | 1 | -1/+1 |
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| * | Added "stat -width" | Clifford Wolf | 2014-08-22 | 1 | -4/+37 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
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| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Bugfixes in new "stat" command | Clifford Wolf | 2013-11-25 | 1 | -7/+1 |
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| * | Added "stat" command | Clifford Wolf | 2013-11-25 | 1 | -0/+218 |
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