Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Fixed "stat" handling of blackbox modules | Clifford Wolf | 2015-02-14 | 1 | -9/+6 |
* | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -5/+5 |
* | sort cell types in "stat" output by name | Clifford Wolf | 2014-10-03 | 1 | -2/+2 |
* | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -113/+114 |
* | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 | 1 | -1/+1 |
* | Added "stat -width" | Clifford Wolf | 2014-08-22 | 1 | -4/+37 |
* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
* | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
* | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
* | Bugfixes in new "stat" command | Clifford Wolf | 2013-11-25 | 1 | -7/+1 |
* | Added "stat" command | Clifford Wolf | 2013-11-25 | 1 | -0/+218 |