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* stat: add option for machine-readable json outputLofty2022-08-111-38/+109
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* also make 'stat' save counts to scratchpadN. Engelhardt2022-06-011-0/+9
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* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-281-0/+4
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* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-021-1/+1
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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* use the new isPublic() in a few placesN. Engelhardt2020-09-141-1/+1
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* Add new builtin FF typesMarcelina Kościelnicka2020-06-231-1/+4
| | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits).
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
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* Add flooring division operatorXiretza2020-05-281-1/+1
| | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* Add flooring modulo operatorXiretza2020-05-281-1/+1
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* Clean up `passes/cmds/stat.cc`.Alberto Gonzalez2020-04-061-26/+20
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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-17/+17
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* kernel: use more ID::*Eddie Hung2020-04-021-5/+5
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* Tweak default gate costs, cleanup "stat -tech cmos"Clifford Wolf2019-08-071-16/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "stat -tech cmos"Clifford Wolf2019-07-201-2/+29
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typoClifford Wolf2019-06-201-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "stat -tech xilinx"Clifford Wolf2019-05-111-3/+73
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Include module name for area summary statsEdmond Cote2018-06-181-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | The PR prints the name of the module when displaying the final area count. Pros: - Easier for the user to `grep` for area information about a specific module Cons: - Arguably more verbose, less "pretty" than author desires Verification: ~~~~ 30c30 < Chip area for this module: 20616.349000 --- > Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000 70c70 < Chip area for this module: 88.697700 --- > Chip area for module '\picorv32_axi_adapter': 88.697700 102c102 < Chip area for this module: 20705.046700 --- > Chip area for top module '\picorv32_axi': 20705.046700 ~~~~
* Add support for "yosys -E"Clifford Wolf2018-01-071-0/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $alu to list of supported cells for "stat -width"Clifford Wolf2017-07-141-1/+1
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* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
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* Added "stat -liberty" for calculating chip areaClifford Wolf2016-02-041-6/+60
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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
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* improvement in "stat"Clifford Wolf2015-10-241-1/+1
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* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
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* Fixed "stat" handling of blackbox modulesClifford Wolf2015-02-141-9/+6
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-5/+5
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* sort cell types in "stat" output by nameClifford Wolf2014-10-031-2/+2
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* namespace YosysClifford Wolf2014-09-271-113/+114
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* Removed $bu0 cell typeClifford Wolf2014-09-041-1/+1
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* Added "stat -width"Clifford Wolf2014-08-221-4/+37
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-3/+3
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
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* Bugfixes in new "stat" commandClifford Wolf2013-11-251-7/+1
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* Added "stat" commandClifford Wolf2013-11-251-0/+218
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