aboutsummaryrefslogtreecommitdiffstats
path: root/passes/hierarchy/hierarchy.cc
Commit message (Collapse)AuthorAgeFilesLines
* Reorder steps in -auto-top to fix synth command, fixes #3261Miodrag Milanovic2022-04-051-13/+13
|
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-0/+4
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-251-1/+1
| | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
* Use new read_id_num helper function elsewhere in hierarchy.ccRupert Swarbrick2021-07-201-5/+6
|
* Extract connection checking logic from expand_module in hierarchy.ccRupert Swarbrick2021-07-201-23/+64
| | | | | No functional change, but pulls more logic out of the expand_module function.
* Extract missing module support in hierarchy.cc to a helper functionRupert Swarbrick2021-07-141-44/+68
| | | | | | | | | | I think the code is now a bit easier to follow (and has lost some levels of indentation!). The only non-trivial change is that I removed the check for cell->type[0] != '$' when deciding whether to complain if we couldn't find a module. This will always be true because of the early exit earlier in the function.
* Move interface expansion in hierarchy.cc into a helper classRupert Swarbrick2021-06-161-100/+189
| | | | | | | | | | | | There should be no functional change, but this splits up the control flow across functions, using class fields to hold the state that's being tracked. The result should be a bit easier to read. This is part of work to add bind support, but I'm doing some refactoring in the hierarchy pass to make the code a bit easier to work with. The idea is that (eventually) the IFExpander object will hold all the logic for expanding interfaces, and then other code can do bind insertion.
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Sign extend port connections where necessaryZachary Snow2020-12-181-2/+6
| | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
* Validate parameters only when they are usedMiodrag Milanovic2020-09-251-5/+7
|
* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-261-1/+1
| | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
|
* Merge pull request #2089 from rswarbrick/modportsclairexen2020-06-081-13/+6
|\ | | | | Simplify a modport check in hierarchy.cc
| * Simplify a modport check in hierarchy.ccRupert Swarbrick2020-05-261-13/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code originally comes from commit 458a940. When an interface is used via a modport, code in genrtlil.cc sets '\\interface_type' and '\\interface_modport' properties on the wire. In hierarchy.cc, we pick up the modport name and add it to a dict called modports_used_in_submodule (that maps connection source to modport name). Before this patch, the modport name is retrieved as a strpool and then iterated over in an arbitrary order, discarding all entries but the last. In practice, the pool will always have 0 or 1 entries because the string used to construct it is a valid identifier, so doesn't contain any pipe symbols. This patch changes the code to retrieve the modport name as just a string. This will have the same effect in practice, but may be a bit less confusing! The code also gets moved down closer to where the result is used, which might be a bit more efficient since we won't always get as far as the check. The patch also removes some commented-out code, which I think was intended to add some typechecking at some point, but was never implemented. Since this dates back to October 2018, I think it makes more sense to just take it out.
* | Fix small typos in documentation for hierarchy commandRupert Swarbrick2020-05-281-2/+2
|/
* hierarchy: Convert positional parameters to named.Marcelina Kościelnicka2020-04-211-3/+27
| | | | Fixes #1821.
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-18/+18
|
* kernel: use more ID::*Eddie Hung2020-04-021-20/+20
|
* Fix double deletion in `passes/hierarchy/hierarchy.cc`.Alberto Gonzalez2020-03-301-1/+0
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.Alberto Gonzalez2020-03-191-68/+63
|
* sv: Improve handling of wildcard port connectionsDavid Shah2020-02-021-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* hierarchy: Correct handling of wildcard port connections with default valuesDavid Shah2020-02-021-7/+14
| | | | Signed-off-by: David Shah <dave@ds0.me>
* hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-021-3/+62
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Adopt @cliffordwolf's suggestionEddie Hung2019-09-031-10/+3
|
* -auto-top should check $abstract (deferred) modules with (* top *)Eddie Hung2019-08-281-0/+31
|
* stoi -> atoiEddie Hung2019-08-071-3/+3
|
* IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
|
* Fix typosEddie Hung2019-08-061-5/+5
|
* Use IdString::begins_with()Eddie Hung2019-08-061-11/+9
|
* Use input default values in hierarchy passClifford Wolf2019-06-191-0/+38
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor hierarchy wand/wor handlingClifford Wolf2019-05-281-102/+143
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-1/+77
|
* Add "hierarchy -chparam" support for non-verific top modulesClifford Wolf2019-05-031-12/+35
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* log_warning_noprefix -> log_warning as per reviewEddie Hung2019-05-031-1/+1
|
* WIP -chparam support for hierarchy when verificEddie Hung2019-05-031-7/+24
|
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-5/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-021-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant ↵Clifford Wolf2019-02-241-5/+1
| | | | | | to -check Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Address requested changes - don't require non-$ name.Jim Lawson2019-02-221-7/+7
| | | | | | Suppress warning if name does begin with a `$`. Fix hierachy tests so they have something to grep. Announce hierarchy test types.
* Fix normal (non-array) hierarchy -auto-top.Jim Lawson2019-02-191-9/+9
| | | | Add simple test.
* Define basic_cell_type() function and use it to derive the cell type for ↵Jim Lawson2019-02-151-10/+40
| | | | array references (instead of duplicating the code).
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-201-2/+5
|
* Support for SystemVerilog interfaces as a port in the top level module + ↵Ruben Undheim2018-10-201-5/+36
| | | | test case
* Documentation improvements etc.Ruben Undheim2018-10-131-27/+38
| | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+13
|
* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-7/+165
| | | | This time doing the changes mostly in AST before RTLIL generation
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Add automatic verific import in hierarchy commandClifford Wolf2018-06-201-1/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in handling of array instances with empty portsClifford Wolf2018-05-311-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 23:33:44 +0000