| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #1519 from YosysHQ/eddie/submod_po | Claire Wolf | 2020-03-03 | 1 | -37/+99 |
| |\ | | | | | submod: several bugfixes | ||||
| | * | Use pool instead of std::set for determinism | Eddie Hung | 2019-12-02 | 1 | -1/+1 |
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| | * | Move \init signal for non-port signals as long as internally driven | Eddie Hung | 2019-11-28 | 1 | -1/+1 |
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| | * | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 |
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| | * | Do not replace constants with same wire | Eddie Hung | 2019-11-27 | 1 | -7/+3 |
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| | * | Cleanup | Eddie Hung | 2019-11-27 | 1 | -5/+3 |
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| | * | Check for nullptr | Eddie Hung | 2019-11-27 | 1 | -1/+1 |
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| | * | Stray log_dump | Eddie Hung | 2019-11-27 | 1 | -1/+0 |
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| | * | Revert "submod to bitty rather bussy, for bussy wires used as input and output" | Eddie Hung | 2019-11-27 | 1 | -40/+71 |
| | | | | | | | | | This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45. | ||||
| | * | Promote output wires in sigmap so that can be detected | Eddie Hung | 2019-11-26 | 1 | -8/+4 |
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| | * | Fix submod -hidden | Eddie Hung | 2019-11-26 | 1 | -5/+6 |
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| | * | Add -hidden option to submod | Eddie Hung | 2019-11-26 | 1 | -11/+25 |
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| | * | Update docs with bullet points | Eddie Hung | 2019-11-26 | 1 | -10/+9 |
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| | * | Move \init from source wire to submod if output port | Eddie Hung | 2019-11-25 | 1 | -0/+7 |
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| | * | submod to bitty rather bussy, for bussy wires used as input and output | Eddie Hung | 2019-11-22 | 1 | -48/+39 |
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| | * | Constant driven signals are also an input to submodules | Eddie Hung | 2019-11-22 | 1 | -2/+10 |
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| | * | Oops | Eddie Hung | 2019-11-22 | 1 | -1/+0 |
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| | * | sigmap(wire) should inherit port_output status of POs | Eddie Hung | 2019-11-22 | 1 | -1/+19 |
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| * | | sv: Improve handling of wildcard port connections | David Shah | 2020-02-02 | 1 | -3/+3 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | hierarchy: Correct handling of wildcard port connections with default values | David Shah | 2020-02-02 | 1 | -7/+14 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | hierarchy: Resolve SV wildcard port connections | David Shah | 2020-02-02 | 1 | -3/+62 |
| |/ | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Adopt @cliffordwolf's suggestion | Eddie Hung | 2019-09-03 | 1 | -10/+3 |
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| * | -auto-top should check $abstract (deferred) modules with (* top *) | Eddie Hung | 2019-08-28 | 1 | -0/+31 |
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| * | stoi -> atoi | Eddie Hung | 2019-08-07 | 1 | -3/+3 |
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| * | IdString::str().substr() -> IdString::substr() | Eddie Hung | 2019-08-06 | 1 | -1/+1 |
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| * | Fix typos | Eddie Hung | 2019-08-06 | 1 | -5/+5 |
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| * | Use IdString::begins_with() | Eddie Hung | 2019-08-06 | 1 | -11/+9 |
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| * | Use input default values in hierarchy pass | Clifford Wolf | 2019-06-19 | 1 | -0/+38 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Refactor hierarchy wand/wor handling | Clifford Wolf | 2019-05-28 | 1 | -102/+143 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | move wand/wor resolution into hierarchy pass | Stefan Biereigel | 2019-05-27 | 1 | -1/+77 |
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| * | Add "hierarchy -chparam" support for non-verific top modules | Clifford Wolf | 2019-05-03 | 1 | -12/+35 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | log_warning_noprefix -> log_warning as per review | Eddie Hung | 2019-05-03 | 1 | -1/+1 |
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| * | WIP -chparam support for hierarchy when verific | Eddie Hung | 2019-05-03 | 1 | -7/+24 |
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| * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 2 | -6/+6 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "hdlname" attribute | Clifford Wolf | 2019-03-26 | 1 | -0/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Only run derive on blackbox modules when ports have dynamic size | Clifford Wolf | 2019-03-02 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant ↵ | Clifford Wolf | 2019-02-24 | 1 | -5/+1 |
| | | | | | | | to -check Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Address requested changes - don't require non-$ name. | Jim Lawson | 2019-02-22 | 1 | -7/+7 |
| | | | | | | | Suppress warning if name does begin with a `$`. Fix hierachy tests so they have something to grep. Announce hierarchy test types. | ||||
| * | Fix normal (non-array) hierarchy -auto-top. | Jim Lawson | 2019-02-19 | 1 | -9/+9 |
| | | | | | Add simple test. | ||||
| * | Define basic_cell_type() function and use it to derive the cell type for ↵ | Jim Lawson | 2019-02-15 | 1 | -10/+40 |
| | | | | | array references (instead of duplicating the code). | ||||
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -1/+1 |
| | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | ||||
| * | Refactor code to avoid code duplication + added comments | Ruben Undheim | 2018-10-20 | 1 | -2/+5 |
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| * | Support for SystemVerilog interfaces as a port in the top level module + ↵ | Ruben Undheim | 2018-10-20 | 1 | -5/+36 |
| | | | | | test case | ||||
| * | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 1 | -27/+38 |
| | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport) | ||||
| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -1/+13 |
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| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -7/+165 |
| | | | | | This time doing the changes mostly in AST before RTLIL generation | ||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 3 | -6/+6 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Add automatic verific import in hierarchy command | Clifford Wolf | 2018-06-20 | 1 | -1/+19 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Bugfix in handling of array instances with empty ports | Clifford Wolf | 2018-05-31 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "hierarchy -simcheck" | Clifford Wolf | 2018-05-12 | 1 | -7/+23 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
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index : iCE40/yosys | |
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