| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -1/+13 | |
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| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -7/+165 | |
| | | | | | This time doing the changes mostly in AST before RTLIL generation | |||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 3 | -6/+6 | |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | |||||
| * | Add automatic verific import in hierarchy command | Clifford Wolf | 2018-06-20 | 1 | -1/+19 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Bugfix in handling of array instances with empty ports | Clifford Wolf | 2018-05-31 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "hierarchy -simcheck" | Clifford Wolf | 2018-05-12 | 1 | -7/+23 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Chenged "extensions_map" to "extensions_list" in hierarchy.cc | Clifford Wolf | 2018-03-27 | 1 | -2/+2 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | passes/hierarchy: Reduce code duplication in expand_module | Sergi Granell | 2018-03-27 | 1 | -15/+13 | |
| | | | | | | | This also makes it easier to add new file extensions support. Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com> | |||||
| * | Add .sv support to "hierarchy -libdir" | Clifford Wolf | 2018-03-26 | 1 | -0/+6 | |
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| * | Bugfix in hierarchy blackbox module port width handling | Clifford Wolf | 2018-01-07 | 1 | -1/+2 | |
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| * | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 1 | -5/+4 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Temporarily derive blackbox modules in hierarchy to evaluate port widths | Clifford Wolf | 2018-01-04 | 1 | -1/+14 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Rename "singleton" pass to "uniquify" | Clifford Wolf | 2017-08-20 | 2 | -20/+21 | |
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| * | Add error for cell output ports that are connected to constants | Clifford Wolf | 2017-07-22 | 1 | -20/+21 | |
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| * | Fix handling of empty cell port assignments (i.e. ignore them) | Clifford Wolf | 2017-07-21 | 1 | -0/+3 | |
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| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -1/+1 | |
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| * | Do not fix port widths on any blackbox instances | Clifford Wolf | 2017-02-13 | 1 | -1/+1 | |
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| * | Do not eagerly fix port widths on parameterized cells | Clifford Wolf | 2017-02-12 | 1 | -0/+3 | |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -1/+1 | |
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| * | passes/hierarchy: delete some dead code | Austin Seipp | 2017-01-15 | 1 | -4/+0 | |
| | | | | | Signed-off-by: Austin Seipp <aseipp@pobox.com> | |||||
| * | Added cell port resizing to hierarchy pass | Clifford Wolf | 2017-01-01 | 1 | -0/+56 | |
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| * | Added support for hierarchical defparams | Clifford Wolf | 2016-11-15 | 1 | -1/+1 | |
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| * | Minor bugfix in submod | Clifford Wolf | 2016-11-09 | 1 | -0/+1 | |
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| * | Bugfix in "hierarchy -check" | Clifford Wolf | 2016-11-02 | 1 | -1/+1 | |
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| * | Added avail params to ilang format, check module params in 'hierarchy -check' | Clifford Wolf | 2016-10-22 | 1 | -0/+4 | |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -1/+1 | |
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| * | Fixed use-after-free dict<> usage pattern in hierarchy.cc | Clifford Wolf | 2016-08-16 | 1 | -1/+3 | |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -1/+1 | |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -1/+1 | |
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| * | Made the expansion order of hierarchy deterministic | Marcus Comstedt | 2016-05-22 | 1 | -3/+3 | |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 3 | -8/+8 | |
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| * | Cleanup abstract modules at end of "hierarchy -top" | Clifford Wolf | 2016-03-21 | 1 | -2/+0 | |
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| * | Added "submod -copy" | Clifford Wolf | 2016-01-08 | 1 | -13/+28 | |
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| * | Added "singleton" pass | Clifford Wolf | 2015-11-07 | 2 | -0/+102 | |
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| * | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -5/+5 | |
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| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -1/+1 | |
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| * | Keep modules with $assume (like $assert) | Clifford Wolf | 2015-07-25 | 1 | -1/+1 | |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 2 | -5/+5 | |
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| * | Added "dffinit", Support for initialized Xilinx DFF | Clifford Wolf | 2015-04-04 | 1 | -2/+2 | |
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| * | documentation improvements | Clifford Wolf | 2015-03-29 | 1 | -1/+1 | |
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| * | Added hierarchy -auto-top | Clifford Wolf | 2015-03-18 | 1 | -1/+33 | |
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| * | Fixed bug in "hierarchy" for parametric designs | Clifford Wolf | 2015-03-04 | 1 | -20/+19 | |
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| * | Cosmetic fixes in "hierarchy" for blackbox modules | Clifford Wolf | 2015-02-15 | 1 | -2/+4 | |
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| * | Fixed pattern matching in "hierarchy -generate" | Clifford Wolf | 2015-01-04 | 1 | -2/+2 | |
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| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -2/+2 | |
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| * | Fixed off-by-one bug in "hierarchy -check" for positional module args | Clifford Wolf | 2014-12-24 | 1 | -2/+2 | |
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| * | Checking existence of ports in "hierarchy -check" | Clifford Wolf | 2014-12-19 | 1 | -0/+13 | |
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| * | Fixed bug in "hierarchy -top" with array of instances | Clifford Wolf | 2014-11-27 | 1 | -3/+10 | |
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| * | Added log_warning() API | Clifford Wolf | 2014-11-09 | 1 | -2/+2 | |
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| * | Various win32 / vs build fixes | Clifford Wolf | 2014-10-17 | 1 | -2/+2 | |
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index : iCE40/yosys | |
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