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* FfData: some refactoring.Marcelina Kościelnicka2021-10-071-1/+1
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-021-7/+15
| | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
* Add opt_mem_widen pass.Marcelina Kościelnicka2021-08-141-0/+2
| | | | If all of us are wide, then none of us are!
* memory_share: Add -nosat and -nowiden options.Marcelina Kościelnicka2021-08-142-10/+41
| | | | This unlocks wide port recognition by default.
* memory_dff: Recognize soft transparency logic.Marcelina Kościelnicka2021-08-131-7/+451
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* Add new opt_mem_priority pass.Marcelina Kościelnicka2021-08-131-2/+4
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* memory_share: Pass addresses through sigmap_xmux everywhere.Marcelina Kościelnicka2021-08-131-20/+25
| | | | This fixes wide port recognition in some cases.
* memory_dff: Recognize read ports with reset / initial value.Marcelina Kościelnicka2021-08-111-7/+0
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* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-113-69/+42
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* Refactor common parts of SAT-using optimizations into a helper.Marcelina Kościelnicka2021-08-091-61/+10
| | | | | | | | | | | | | This also aligns the functionality: - in all cases, the onehot attribute is used to create appropriate constraints (previously, opt_dff didn't do it at all, and share created one-hot constraints based on $pmux presence alone, which is unsound) - in all cases, shift and mul/div/pow cells are now skipped when importing the SAT problem (previously only memory_share did this) — this avoids creating clauses for hard cells that are unlikely to help with proving the UNSATness needed for optimization
* memory_share: Don't skip ports with EN wired to input for SAT sharing.Marcelina Kościelnicka2021-08-041-3/+1
| | | | Fixes #2912.
* memory_bram: Move init data swizzling before other swizzling.Marcelina Kościelnicka2021-08-031-18/+18
| | | | Fixes #2907.
* memory_bram: Some refactoringMarcelina Kościelnicka2021-08-011-196/+174
| | | | | | This will make more sense when the new transparency masks land. Fixes #2902.
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-089-9/+9
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* memory_map: Improve start_offset handling.Marcelina Kościelnicka2021-05-311-35/+31
| | | | Fixes #2775.
* memory_share: Add read port merging.Marcelina Kościelnicka2021-05-291-0/+140
| | | | | This is mostly meant for wide port recognition, but may also happen to merge some ports with compatible initial/reset values (eg. 0 vs x).
* memory_share: Improve sat-based port sharing.Marcelina Kościelnicka2021-05-281-117/+151
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* Make a few passes auto-call Mem::narrow instead of rejecting wide ports.Marcelina Kościelnicka2021-05-281-14/+1
| | | | | | This essentially adds wide port support for free in passes that don't have a usefully better way of handling wide ports than just breaking them up to narrow ports, avoiding "please run memory_narrow" annoyance.
* memory_share: Improve same-address merging, recognize wide write ports.Marcelina Kościelnicka2021-05-271-204/+77
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* mem/extract_rdff: Fix "no FF made" edge case.Marcelina Kościelnicka2021-05-251-2/+5
| | | | | | | When converting a sync transparent read port with const address to async read port, nothing at all needs to be done other than clk_enable change, and thus we have no FF cell to return. Handle this case correctly in the helper and in its users.
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-251-23/+38
| | | | | Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
* memory_bram: Respect write port priority.Marcelina Kościelnicka2021-05-251-0/+14
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* Add memory_narrow pass.Marcelina Kościelnicka2021-05-252-0/+68
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* memory_share: Add wide port support.Marcelina Kościelnicka2021-05-251-0/+6
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* memory_map: Add wide port support.Marcelina Kościelnicka2021-05-251-16/+17
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* Reject wide ports in some passes that will never support them.Marcelina Kościelnicka2021-05-251-0/+14
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* memory_share: Use Mem helpers.Marcelina Kościelnicka2021-05-231-89/+71
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* extract_rdff: Add initvals parameter.Marcelina Kościelnicka2021-05-232-9/+15
| | | | | This is not used yet, but will be needed when read port reset/initial value support lands.
* memory_share: Split off feedback path finding as a separate pass.Marcelina Kościelnicka2021-05-232-242/+9
| | | | | memory_share is actually three passes in a trenchcoat. Split off the one that has the least in common with the other two as a separate pass.
* Add new helper class for merging FFs into cells, use for memory_dff.Marcelina Kościelnicka2021-05-231-237/+104
| | | | Fixes #1854.
* memory_memx: Use Mem helper.Marcelina Kościelnicka2021-05-221-42/+31
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* memory_dff: Use Mem helper.Marcelina Kościelnicka2021-05-211-19/+26
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* memory_dff: Remove now-useless write port handling.Marcelina Kościelnicka2021-03-083-74/+11
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* memory_dff: Remove code looking for $mux cells.Marcelina Kościelnicka2021-03-081-56/+12
| | | | This job is now performed by `opt_dff`, which runs before this pass.
* memory_dff: Fix needlessly duplicating enable bits.Marcelina Kościelnicka2020-10-221-0/+8
| | | | | | | | | When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409.
* memory_bram: Use Mem helpers.Marcelina Kościelnicka2020-10-211-121/+90
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* memory_map: Use Mem helpers.Marcelina Kościelnicka2020-10-211-138/+81
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* memory_unpack: Use Mem helpers.Marcelina Kościelnicka2020-10-211-106/+10
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* memory_collect: Use Mem helpers.Marcelina Kościelnicka2020-10-211-223/+9
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* memory_nordff: Use Mem helpers.Marcelina Kościelnicka2020-10-211-63/+9
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* memory_dff: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-12/+5
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* memory_dff: recognize more dff cellsMarcelina Kościelnicka2020-07-231-11/+112
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* Use C++11 final/override keywords.whitequark2020-06-189-18/+18
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* Add flooring division operatorXiretza2020-05-281-0/+1
| | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* Add flooring modulo operatorXiretza2020-05-281-0/+1
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* memory_bram: Fix ignorance of valid, matched rulesDavid Shah2020-04-101-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-102-13/+148
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * memory_map: add -attr option, to respect inference attributes.whitequark2020-04-031-6/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, memory_map (which is always a part of a synth script) would always pick up any $mem cell that was not processed by a preceding pass and lower it down to $dff/$mux cells. This is undesirable for two reasons: * If there is an explicit inference attribute set on a $mem cell, e.g. (* ram_block *), then it is arguably incorrect to map such a memory to $dff/$mux cells. * If memory_map tries to lower a memory that was intended to be mapped to a large BRAM, it often takes extraordinarily long time to finish, produces an extremely large log file, and outputs an unusable design. After this commit, properly invoked memory_map will not map any memory that has an explicit inference attribute specified, solving the first issue, and alleviating the second. The default behavior is not changed.
| * memory_bram: add `attr_icase` option.whitequark2020-02-061-7/+35
| | | | | | | | | | Some vendor toolchains use case insensitive matching for values of attributes that control BRAM inference.
* | Merge pull request #1890 from boqwxp/cleanup_memory_collectN. Engelhardt2020-04-091-6/+3
|\ \ | | | | | | Clean up `passes/memory/memory_collect.cc`.
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